diff options
| author | Marek Olšák <[email protected]> | 2018-09-21 03:36:32 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2018-10-16 15:28:22 -0400 |
| commit | 6e1cf6532dc7a498a6a04e9fd5f8147aec0d2030 (patch) | |
| tree | 6b08c95f73a203ed46c446bb77a26a30ddef5c6f /src/gallium/drivers/radeonsi/si_fence.c | |
| parent | 0fa9e6d7b304f6a8064ed78a4b9c557e1026e7e5 (diff) | |
radeonsi: make si_gfx_write_event_eop more configurable
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_fence.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_fence.c | 23 |
1 files changed, 13 insertions, 10 deletions
diff --git a/src/gallium/drivers/radeonsi/si_fence.c b/src/gallium/drivers/radeonsi/si_fence.c index abb7057f299..f1e0fac230b 100644 --- a/src/gallium/drivers/radeonsi/si_fence.c +++ b/src/gallium/drivers/radeonsi/si_fence.c @@ -58,7 +58,9 @@ struct si_multi_fence { * * \param event EVENT_TYPE_* * \param event_flags Optional cache flush flags (TC) - * \param data_sel 1 = fence, 3 = timestamp + * \param dst_sel MEM or TC_L2 + * \param int_sel NONE or SEND_DATA_AFTER_WR_CONFIRM + * \param data_sel DISCARD, VALUE_32BIT, TIMESTAMP, or GDS * \param buf Buffer * \param va GPU address * \param old_value Previous fence value (for a bug workaround) @@ -66,20 +68,18 @@ struct si_multi_fence { */ void si_gfx_write_event_eop(struct si_context *ctx, unsigned event, unsigned event_flags, - unsigned data_sel, + unsigned dst_sel, unsigned int_sel, unsigned data_sel, struct r600_resource *buf, uint64_t va, uint32_t new_fence, unsigned query_type) { struct radeon_cmdbuf *cs = ctx->gfx_cs; unsigned op = EVENT_TYPE(event) | - EVENT_INDEX(5) | + EVENT_INDEX(event == V_028A90_CS_DONE || + event == V_028A90_PS_DONE ? 6 : 5) | event_flags; - unsigned sel = EOP_DATA_SEL(data_sel); - - /* Wait for write confirmation before writing data, but don't send - * an interrupt. */ - if (data_sel != EOP_DATA_SEL_DISCARD) - sel |= EOP_INT_SEL(EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM); + unsigned sel = EOP_DST_SEL(dst_sel) | + EOP_INT_SEL(int_sel) | + EOP_DATA_SEL(data_sel); if (ctx->chip_class >= GFX9) { /* A ZPASS_DONE or PIXEL_STAT_DUMP_EVENT (of the DB occlusion @@ -275,7 +275,10 @@ static void si_fine_fence_set(struct si_context *ctx, radeon_emit(cs, fence_va >> 32); radeon_emit(cs, 0x80000000); } else if (flags & PIPE_FLUSH_BOTTOM_OF_PIPE) { - si_gfx_write_event_eop(ctx, V_028A90_BOTTOM_OF_PIPE_TS, 0, + si_gfx_write_event_eop(ctx, + V_028A90_BOTTOM_OF_PIPE_TS, 0, + EOP_DST_SEL_MEM, + EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM, EOP_DATA_SEL_VALUE_32BIT, NULL, fence_va, 0x80000000, PIPE_QUERY_GPU_FINISHED); |