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authorMichel Dänzer <[email protected]>2014-04-21 18:23:38 +0900
committerMichel Dänzer <[email protected]>2014-04-22 12:07:07 +0900
commit360038fa5028b32837580478d36e5ec2c54d8652 (patch)
tree5b742f1f5e4713a7dd776feae8acab321d5fe4b9 /src/gallium/drivers/radeonsi/si_dma.c
parent0dfa6e7cf5a1f5207b32140f48cd3870db8a189b (diff)
radeonsi: Fix calculation of number of banks for SI
The way cik_num_banks() was calculating the index only makes sense for the CIK specific macrotile mode array. For SI, we need to use the tile mode index directly. This happened to work most of the time because most of the SI tiling modes use the same number of banks. Reviewed-by: Marek Olšák <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_dma.c')
-rw-r--r--src/gallium/drivers/radeonsi/si_dma.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeonsi/si_dma.c b/src/gallium/drivers/radeonsi/si_dma.c
index 97ea08b8f8f..dc8c609b8d9 100644
--- a/src/gallium/drivers/radeonsi/si_dma.c
+++ b/src/gallium/drivers/radeonsi/si_dma.c
@@ -169,10 +169,11 @@ static void si_dma_copy_tile(struct si_context *ctx,
bank_h = cik_bank_wh(rsrc->surface.bankh);
bank_w = cik_bank_wh(rsrc->surface.bankw);
mt_aspect = cik_macro_tile_aspect(rsrc->surface.mtilea);
- nbanks = cik_num_banks(sscreen, rsrc->surface.bpe, rsrc->surface.tile_split);
tile_split = cik_tile_split(rsrc->surface.tile_split);
tile_mode_index = si_tile_mode_index(rsrc, src_level,
util_format_has_stencil(util_format_description(src->format)));
+ nbanks = si_num_banks(sscreen, rsrc->surface.bpe, rsrc->surface.tile_split,
+ tile_mode_index);
base += r600_resource_va(&ctx->screen->b.b, src);
addr += r600_resource_va(&ctx->screen->b.b, dst);
} else {
@@ -197,10 +198,11 @@ static void si_dma_copy_tile(struct si_context *ctx,
bank_h = cik_bank_wh(rdst->surface.bankh);
bank_w = cik_bank_wh(rdst->surface.bankw);
mt_aspect = cik_macro_tile_aspect(rdst->surface.mtilea);
- nbanks = cik_num_banks(sscreen, rdst->surface.bpe, rdst->surface.tile_split);
tile_split = cik_tile_split(rdst->surface.tile_split);
tile_mode_index = si_tile_mode_index(rdst, dst_level,
util_format_has_stencil(util_format_description(dst->format)));
+ nbanks = si_num_banks(sscreen, rdst->surface.bpe, rdst->surface.tile_split,
+ tile_mode_index);
base += r600_resource_va(&ctx->screen->b.b, dst);
addr += r600_resource_va(&ctx->screen->b.b, src);
}