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authorMarek Olšák <[email protected]>2017-06-05 19:51:38 +0200
committerMarek Olšák <[email protected]>2017-06-07 19:38:39 +0200
commitd2ee423b69660a219c031abad101decd0ecae327 (patch)
tree3414d58d95f398ed714fb1f75ed5c93fba4830dd /src/gallium/drivers/radeonsi/si_descriptors.c
parente003e3c4c058e69e3dcaee3d31493b27ffc0052c (diff)
radeonsi: enable TC-compatible stencil compression on VI
Most things are in place. Ideally we won't see decompress blits for stencil anymore. Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_descriptors.c')
-rw-r--r--src/gallium/drivers/radeonsi/si_descriptors.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 61eb2f10be2..7a2b71df6b5 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -339,8 +339,7 @@ static void si_sampler_view_add_buffer(struct si_context *sctx,
}
if (rtex->htile_buffer &&
- rtex->tc_compatible_htile &&
- !is_stencil_sampler) {
+ rtex->tc_compatible_htile) {
radeon_add_to_buffer_list_check_mem(&sctx->b, &sctx->b.gfx,
rtex->htile_buffer, usage,
RADEON_PRIO_HTILE, check_mem);
@@ -424,7 +423,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
if (sscreen->b.chip_class <= VI)
meta_va += base_level_info->dcc_offset;
- } else if (tex->tc_compatible_htile && !is_stencil) {
+ } else if (tex->tc_compatible_htile) {
meta_va = tex->htile_buffer->gpu_address;
}
@@ -571,7 +570,8 @@ static bool depth_needs_decompression(struct r600_texture *rtex,
struct si_sampler_view *sview)
{
return rtex->db_compatible &&
- (!rtex->tc_compatible_htile || sview->is_stencil_sampler);
+ (!rtex->tc_compatible_htile ||
+ !r600_can_sample_zs(rtex, sview->is_stencil_sampler));
}
static void si_update_compressed_tex_shader_mask(struct si_context *sctx,