diff options
| author | Alex Deucher <[email protected]> | 2012-10-01 16:37:54 -0400 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2013-06-28 15:16:35 -0400 |
| commit | 72c10be3a76e0e63a6e33da148fd755a1e3f34c1 (patch) | |
| tree | 74e0eb17cb2ca1646c51e8d0afada2a8116d2dea /src/gallium/drivers/radeonsi/si_commands.c | |
| parent | f2a9bd80840d5c570689ea1f4ccb648000fc9b88 (diff) | |
radeonsi: update surface sync packet emit for CIK
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_commands.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_commands.c | 23 |
1 files changed, 17 insertions, 6 deletions
diff --git a/src/gallium/drivers/radeonsi/si_commands.c b/src/gallium/drivers/radeonsi/si_commands.c index 8dcf5d3341b..bf9592493c3 100644 --- a/src/gallium/drivers/radeonsi/si_commands.c +++ b/src/gallium/drivers/radeonsi/si_commands.c @@ -60,10 +60,21 @@ void si_cmd_draw_index_auto(struct si_pm4_state *pm4, uint32_t count, void si_cmd_surface_sync(struct si_pm4_state *pm4, uint32_t cp_coher_cntl) { - si_pm4_cmd_begin(pm4, PKT3_SURFACE_SYNC); - si_pm4_cmd_add(pm4, cp_coher_cntl); /* CP_COHER_CNTL */ - si_pm4_cmd_add(pm4, 0xffffffff); /* CP_COHER_SIZE */ - si_pm4_cmd_add(pm4, 0); /* CP_COHER_BASE */ - si_pm4_cmd_add(pm4, 0x0000000A); /* POLL_INTERVAL */ - si_pm4_cmd_end(pm4, false); + if (pm4->chip_class >= CIK) { + si_pm4_cmd_begin(pm4, PKT3_ACQUIRE_MEM); + si_pm4_cmd_add(pm4, cp_coher_cntl); /* CP_COHER_CNTL */ + si_pm4_cmd_add(pm4, 0xffffffff); /* CP_COHER_SIZE */ + si_pm4_cmd_add(pm4, 0xff); /* CP_COHER_SIZE_HI */ + si_pm4_cmd_add(pm4, 0); /* CP_COHER_BASE */ + si_pm4_cmd_add(pm4, 0); /* CP_COHER_BASE_HI */ + si_pm4_cmd_add(pm4, 0x0000000A); /* POLL_INTERVAL */ + si_pm4_cmd_end(pm4, false); + } else { + si_pm4_cmd_begin(pm4, PKT3_SURFACE_SYNC); + si_pm4_cmd_add(pm4, cp_coher_cntl); /* CP_COHER_CNTL */ + si_pm4_cmd_add(pm4, 0xffffffff); /* CP_COHER_SIZE */ + si_pm4_cmd_add(pm4, 0); /* CP_COHER_BASE */ + si_pm4_cmd_add(pm4, 0x0000000A); /* POLL_INTERVAL */ + si_pm4_cmd_end(pm4, false); + } } |