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authorMarek Olšák <[email protected]>2014-09-20 12:02:59 +0200
committerMarek Olšák <[email protected]>2014-09-24 14:48:02 +0200
commitc94486670805be0f12ade6a7a2e5c324db4cb798 (patch)
tree800b82b3aa30d9130ddf3f619e8019ee3b848194 /src/gallium/drivers/radeonsi/si_commands.c
parentdd53d53dc664946a445bcb9e26b1819f4b92a32c (diff)
radeonsi: remove old cache flushing code
Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_commands.c')
-rw-r--r--src/gallium/drivers/radeonsi/si_commands.c21
1 files changed, 0 insertions, 21 deletions
diff --git a/src/gallium/drivers/radeonsi/si_commands.c b/src/gallium/drivers/radeonsi/si_commands.c
index 2efdedaf499..bf1cb301721 100644
--- a/src/gallium/drivers/radeonsi/si_commands.c
+++ b/src/gallium/drivers/radeonsi/si_commands.c
@@ -109,24 +109,3 @@ void si_cmd_draw_index_indirect(struct si_pm4_state *pm4, uint64_t indirect_va,
si_pm4_cmd_add(pm4, V_0287F0_DI_SRC_SEL_DMA);
si_pm4_cmd_end(pm4, predicate);
}
-
-void si_cmd_surface_sync(struct si_pm4_state *pm4, uint32_t cp_coher_cntl)
-{
- if (pm4->chip_class >= CIK) {
- si_pm4_cmd_begin(pm4, PKT3_ACQUIRE_MEM);
- si_pm4_cmd_add(pm4, cp_coher_cntl); /* CP_COHER_CNTL */
- si_pm4_cmd_add(pm4, 0xffffffff); /* CP_COHER_SIZE */
- si_pm4_cmd_add(pm4, 0xff); /* CP_COHER_SIZE_HI */
- si_pm4_cmd_add(pm4, 0); /* CP_COHER_BASE */
- si_pm4_cmd_add(pm4, 0); /* CP_COHER_BASE_HI */
- si_pm4_cmd_add(pm4, 0x0000000A); /* POLL_INTERVAL */
- si_pm4_cmd_end(pm4, false);
- } else {
- si_pm4_cmd_begin(pm4, PKT3_SURFACE_SYNC);
- si_pm4_cmd_add(pm4, cp_coher_cntl); /* CP_COHER_CNTL */
- si_pm4_cmd_add(pm4, 0xffffffff); /* CP_COHER_SIZE */
- si_pm4_cmd_add(pm4, 0); /* CP_COHER_BASE */
- si_pm4_cmd_add(pm4, 0x0000000A); /* POLL_INTERVAL */
- si_pm4_cmd_end(pm4, false);
- }
-}