diff options
| author | Marek Olšák <[email protected]> | 2018-05-02 18:35:27 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2018-05-10 18:39:53 -0400 |
| commit | 8b58a14ef76f6d6e6c71fff2cb5c8fa6662a1882 (patch) | |
| tree | c5e0bfbad7d114c929d5f1e5530d0569b0c6bc03 /src/gallium/drivers/radeonsi/si_clear.c | |
| parent | b81149e258a492ed0c81058fb535f6bfdacb36da (diff) | |
ac/gpu_info: add htile_cmask_support_1d_tiling
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_clear.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_clear.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c index 23977186611..0e2d2f1013b 100644 --- a/src/gallium/drivers/radeonsi/si_clear.c +++ b/src/gallium/drivers/radeonsi/si_clear.c @@ -437,13 +437,10 @@ static void si_do_fast_color_clear(struct si_context *sctx, !(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH)) continue; - /* fast color clear with 1D tiling doesn't work on old kernels and CIK */ - if (sctx->chip_class == CIK && + if (sctx->chip_class <= VI && tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D && - sctx->screen->info.drm_major == 2 && - sctx->screen->info.drm_minor < 38) { + !sctx->screen->info.htile_cmask_support_1d_tiling) continue; - } /* Fast clear is the most appropriate place to enable DCC for * displayable surfaces. |