diff options
| author | Marek Olšák <[email protected]> | 2018-04-01 15:37:11 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2018-04-05 15:34:58 -0400 |
| commit | 884fd97f6b83ac674f158e843941cbea3ca6582b (patch) | |
| tree | cbdb5d01ec9377f0d0d97454437e0a2a336189a4 /src/gallium/drivers/radeonsi/si_clear.c | |
| parent | a8291a23c5fd4f18fe8d8f3acace222e9b04038d (diff) | |
radeonsi: use r600_common_context less pt4
Acked-by: Timothy Arceri <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_clear.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_clear.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c index 464b9d7ac56..59ab9ae4366 100644 --- a/src/gallium/drivers/radeonsi/si_clear.c +++ b/src/gallium/drivers/radeonsi/si_clear.c @@ -407,7 +407,7 @@ static void si_do_fast_color_clear(struct si_context *sctx, */ if (sctx->b.chip_class >= VI && !(sctx->screen->debug_flags & DBG(NO_DCC_FB))) { - vi_separate_dcc_try_enable(&sctx->b, tex); + vi_separate_dcc_try_enable(sctx, tex); /* RB+ isn't supported with a CMASK clear only on Stoney, * so all clears are considered to be hypothetically slow |