diff options
| author | Marek Olšák <[email protected]> | 2014-12-29 14:45:49 +0100 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2015-01-07 12:06:43 +0100 |
| commit | edf18da85dd3b1865c4faaba650a8fa371b7103c (patch) | |
| tree | 5cf04bf87559911e77dd5c57093bb2d64503e390 /src/gallium/drivers/radeonsi/si_blit.c | |
| parent | 73c2b0d18c51459697d8ec194ecfc4438c98c139 (diff) | |
radeonsi: only flush the right set of caches for CP DMA operations
That's either framebuffer caches or caches for shader resources.
The motivation is that framebuffer caches need to be flushed very rarely
here.
Reviewed-by: Michel Dänzer <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_blit.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/si_blit.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c index 4744154c7e2..1f2c4082dbc 100644 --- a/src/gallium/drivers/radeonsi/si_blit.c +++ b/src/gallium/drivers/radeonsi/si_blit.c @@ -556,7 +556,7 @@ void si_resource_copy_region(struct pipe_context *ctx, /* Fallback for buffers. */ if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) { - si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width); + si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width, false); return; } |