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authorMarek Olšák <[email protected]>2017-06-06 23:54:23 +0200
committerMarek Olšák <[email protected]>2017-06-08 23:29:07 +0200
commit69403617963681ed48fa937e978919b855aa4049 (patch)
tree53adc06ea5548244e06dd29432b1a23f1e16e6a5 /src/gallium/drivers/radeonsi/si_blit.c
parentc6451b12096fb4258051b9b38c50ffb0a86df173 (diff)
gallium/radeon: don't allocate HTILE in a separate buffer
Reviewed-by: Samuel Pitoiset <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/si_blit.c')
-rw-r--r--src/gallium/drivers/radeonsi/si_blit.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index e39ba62e0b8..74bc2e9a51a 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -726,7 +726,7 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
}
}
- if (zstex && zstex->htile_buffer &&
+ if (zstex && zstex->htile_offset &&
zsbuf->u.tex.level == 0 &&
zsbuf->u.tex.first_layer == 0 &&
zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {