radeonsi: initial WIP SI code

This commit adds initial support for acceleration
on SI chips.  egltri is starting to work.

The SI/R600 llvm backend is currently included in mesa
but that may change in the future.

The plan is to write a single gallium driver and
use gallium to support X acceleration.

This commit contains patches from:
Tom Stellard <[email protected]>
Michel Dänzer <[email protected]>
Alex Deucher <[email protected]>
Vadim Girlin <[email protected]>

Signed-off-by: Alex Deucher <[email protected]>

The following commits were squashed in:

======================================================================

radeonsi: Remove unused winsys pointer

This was removed from r600g in commit:

commit 96d882939d612fcc8332f107befec470ed4359de
Author: Marek Olšák <[email protected]>
Date:   Fri Feb 17 01:49:49 2012 +0100

    gallium: remove unused winsys pointers in pipe_screen and pipe_context

    A winsys is already a private object of a driver.

======================================================================

radeonsi: Copy color clamping CAPs from r600

Not sure if the values of these CAPS are correct for radeonsi, but the
same changed were made to r600g in commit:

commit bc1c8369384b5e16547c5bf9728aa78f8dfd66cc
Author: Marek Olšák <[email protected]>
Date:   Mon Jan 23 03:11:17 2012 +0100

    st/mesa: do vertex and fragment color clamping in shaders

    For ARB_color_buffer_float. Most hardware can't do it and st/mesa is
    the perfect place for a fallback.
    The exceptions are:
    - r500 (vertex clamp only)
    - nv50 (both)
    - nvc0 (both)
    - softpipe (both)

    We also have to take into account that r300 can do CLAMPED vertex colors only,
    while r600 can do UNCLAMPED vertex colors only. The difference can be expressed
    with the two new CAPs.

======================================================================

radeonsi: Remove PIPE_CAP_OUTPUT_READ

This CAP was dropped in commit:

commit 04e324008759282728a95a1394bac2c4c2a1a3f9
Author: Marek Olšák <[email protected]>
Date:   Thu Feb 23 23:44:36 2012 +0100

    gallium: remove PIPE_SHADER_CAP_OUTPUT_READ

    r600g is the only driver which has made use of it. The reason the CAP was
    added was to fix some piglit tests when the GLSL pass lower_output_reads
    didn't exist.

    However, not removing output reads breaks the fallback for glClampColorARB,
    which assumes outputs are not readable. The fix would be non-trivial
    and my personal preference is to remove the CAP, considering that reading
    outputs is uncommon and that we can now use lower_output_reads to fix
    the issue that the CAP was supposed to workaround in the first place.

======================================================================

radeonsi: Add missing parameters to rws->buffer_get_tiling() call

This was changed in commit:

commit c0c979eebc076b95cc8d18a013ce2968fe6311ad
Author: Jerome Glisse <[email protected]>
Date:   Mon Jan 30 17:22:13 2012 -0500

    r600g: add support for common surface allocator for tiling v13

    Tiled surface have all kind of alignment constraint that needs to
    be met. Instead of having all this code duplicated btw ddx and
    mesa use common code in libdrm_radeon this also ensure that both
    ddx and mesa compute those alignment in the same way.

    v2 fix evergreen
    v3 fix compressed texture and workaround cube texture issue by
       disabling 2D array mode for cubemap (need to check if r7xx and
       newer are also affected by the issue)
    v4 fix texture array
    v5 fix evergreen and newer, split surface values computation from
       mipmap tree generation so that we can get them directly from the
       ddx
    v6 final fix to evergreen tile split value
    v7 fix mipmap offset to avoid to use random value, use color view
       depth view to address different layer as hardware is doing some
       magic rotation depending on the layer
    v8 fix COLOR_VIEW on r6xx for linear array mode, use COLOR_VIEW on
       evergreen, align bytes per pixel to a multiple of a dword
    v9 fix handling of stencil on evergreen, half fix for compressed
       texture
    v10 fix evergreen compressed texture proper support for stencil
        tile split. Fix stencil issue when array mode was clear by
        the kernel, always program stencil bo. On evergreen depth
        buffer bo need to be big enough to hold depth buffer + stencil
        buffer as even with stencil disabled things get written there.
    v11 rebase on top of mesa, fix pitch issue with 1d surface on evergreen,
        old ddx overestimate those. Fix linear case when pitch*height < 64.
        Fix r300g.
    v12 Fix linear case when pitch*height < 64 for old path, adapt to
        libdrm API change
    v13 add libdrm check

    Signed-off-by: Jerome Glisse <[email protected]>

======================================================================

radeonsi: Remove PIPE_TRANSFER_MAP_PERMANENTLY

This was removed in commit:

commit 62f44f670bb0162e89fd4786af877f8da9ff607c
Author: Marek Olšák <[email protected]>
Date:   Mon Mar 5 13:45:00 2012 +0100

    Revert "gallium: add flag PIPE_TRANSFER_MAP_PERMANENTLY"

    This reverts commit 0950086376b1c8b7fb89eda81ed7f2f06dee58bc.

    It was decided to refactor the transfer API instead of adding workarounds
    to address the performance issues.

======================================================================

radeonsi: Handle PIPE_VIDEO_CAP_PREFERED_FORMAT.

Reintroduced in commit 9d9afcb5bac2931d4b8e6d1aa571e941c5110c90.

======================================================================

radeonsi: nuke the fallback for vertex and fragment color clamping

Ported from r600g commit c2b800cf38b299c1ab1c53dc0e4ea00c7acef853.

======================================================================

radeonsi: don't expose transform_feedback2 without kernel support

Ported from r600g commit 15146fd1bcbb08e44a1cbb984440ee1a5de63d48.

======================================================================

radeonsi: Handle PIPE_CAP_GLSL_FEATURE_LEVEL.

Ported from r600g part of commit 171be755223d99f8cc5cc1bdaf8bd7b4caa04b4f.

======================================================================

radeonsi: set minimum point size to 1.0 for non-sprite non-aa points.

Ported from r600g commit f183cc9ce3ad1d043bdf8b38fd519e8f437714fc.

======================================================================

radeonsi: rework and consolidate stencilref state setting.

Ported from r600g commit a2361946e782b57f0c63587841ca41c0ea707070.

======================================================================

radeonsi: cleanup setting DB_SHADER_CONTROL.

Ported from r600g commit 3d061caaed13b646ff40754f8ebe73f3d4983c5b.

======================================================================

radeonsi: Get rid of register masks.

Ported from r600g commits
3d061caaed13b646ff40754f8ebe73f3d4983c5b..9344ab382a1765c1a7c2560e771485edf4954fe2.

======================================================================

radeonsi: get rid of r600_context_reg.

Ported from r600g commits
9344ab382a1765c1a7c2560e771485edf4954fe2..bed20f02a771f43e1c5092254705701c228cfa7f.

======================================================================

radeonsi: Fix regression from 'Get rid of register masks'.

======================================================================

radeonsi: optimize r600_resource_va.

Ported from r600g commit 669d8766ff3403938794eb80d7769347b6e52174.

======================================================================

radeonsi: remove u8,u16,u32,u64 types.

Ported from r600g commit 78293b99b23268e6698f1267aaf40647c17d95a5.

======================================================================

radeonsi: merge r600_context with r600_pipe_context.

Ported from r600g commit e4340c1908a6a3b09e1a15d5195f6da7d00494d0.

======================================================================

radeonsi: Miscellaneous context cleanups.

Ported from r600g commits
e4340c1908a6a3b09e1a15d5195f6da7d00494d0..621e0db71c5ddcb379171064a4f720c9cf01e888.

======================================================================

radeonsi: add a new simple API for state emission.

Ported from r600g commits
621e0db71c5ddcb379171064a4f720c9cf01e888..f661405637bba32c2cfbeecf6e2e56e414e9521e.

======================================================================

radeonsi: Also remove sbu_flags member of struct r600_reg.

Requires using sid.h instead of r600d.h for the new CP_COHER_CNTL definitions,
so some code needs to be disabled for now.

======================================================================

radeonsi: Miscellaneous simplifications.

Ported from r600g commits 38bf2763482b4f1b6d95cd51aecec75601d8b90f and
b0337b679ad4c2feae59215104cfa60b58a619d5.

======================================================================

radeonsi: Handle PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION.

Ported from commit 8b4f7b0672d663273310fffa9490ad996f5b914a.

======================================================================

radeonsi: Use a fake reloc to sleep for fences.

Ported from r600g commit 8cd03b933cf868ff867e2db4a0937005a02fd0e4.

======================================================================

radeonsi: adapt to get_query_result interface change.

Ported from r600g commit 4445e170bee23a3607ece0e010adef7058ac6a11.

1 files changed, 490 insertions, 0 deletions

diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.h b/src/gallium/drivers/radeonsi/radeonsi_pipe.h
new file mode 100644
index 00000000000..f4a1219d860
--- /dev/null
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.h
@@ -0,0 +1,490 @@
+/*
+ * Copyright 2010 Jerome Glisse <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *      Jerome Glisse
+ */
+#ifndef RADEONSI_PIPE_H
+#define RADEONSI_PIPE_H
+
+#include "../../winsys/radeon/drm/radeon_winsys.h"
+
+#include "pipe/p_state.h"
+#include "pipe/p_screen.h"
+#include "pipe/p_context.h"
+#include "util/u_format.h"
+#include "util/u_math.h"
+#include "util/u_slab.h"
+#include "util/u_vbuf.h"
+#include "r600.h"
+#include "radeonsi_public.h"
+#include "r600_resource.h"
+
+#define R600_MAX_CONST_BUFFERS 1
+#define R600_MAX_CONST_BUFFER_SIZE 4096
+
+#ifdef PIPE_ARCH_BIG_ENDIAN
+#define R600_BIG_ENDIAN 1
+#else
+#define R600_BIG_ENDIAN 0
+#endif
+
+enum r600_atom_flags {
+	/* When set, atoms are added at the beginning of the dirty list
+	 * instead of the end. */
+	EMIT_EARLY = (1 << 0)
+};
+
+/* This encapsulates a state or an operation which can emitted into the GPU
+ * command stream. It's not limited to states only, it can be used for anything
+ * that wants to write commands into the CS (e.g. cache flushes). */
+struct r600_atom {
+	void (*emit)(struct r600_context *ctx, struct r600_atom *state);
+
+	unsigned		num_dw;
+	enum r600_atom_flags	flags;
+	bool			dirty;
+
+	struct list_head	head;
+};
+
+struct r600_atom_surface_sync {
+	struct r600_atom atom;
+	unsigned flush_flags; /* CP_COHER_CNTL */
+};
+
+enum r600_pipe_state_id {
+	R600_PIPE_STATE_BLEND = 0,
+	R600_PIPE_STATE_BLEND_COLOR,
+	R600_PIPE_STATE_CONFIG,
+	R600_PIPE_STATE_SEAMLESS_CUBEMAP,
+	R600_PIPE_STATE_CLIP,
+	R600_PIPE_STATE_SCISSOR,
+	R600_PIPE_STATE_VIEWPORT,
+	R600_PIPE_STATE_RASTERIZER,
+	R600_PIPE_STATE_VGT,
+	R600_PIPE_STATE_FRAMEBUFFER,
+	R600_PIPE_STATE_DSA,
+	R600_PIPE_STATE_STENCIL_REF,
+	R600_PIPE_STATE_PS_SHADER,
+	R600_PIPE_STATE_VS_SHADER,
+	R600_PIPE_STATE_CONSTANT,
+	R600_PIPE_STATE_SAMPLER,
+	R600_PIPE_STATE_RESOURCE,
+	R600_PIPE_STATE_POLYGON_OFFSET,
+	R600_PIPE_NSTATES
+};
+
+struct r600_pipe_fences {
+	struct r600_resource		*bo;
+	unsigned			*data;
+	unsigned			next_index;
+	/* linked list of preallocated blocks */
+	struct list_head		blocks;
+	/* linked list of freed fences */
+	struct list_head		pool;
+	pipe_mutex			mutex;
+};
+
+struct r600_screen {
+	struct pipe_screen		screen;
+	struct radeon_winsys		*ws;
+	unsigned			family;
+	enum chip_class			chip_class;
+	struct radeon_info		info;
+	struct r600_tiling_info		tiling_info;
+	struct util_slab_mempool	pool_buffers;
+	struct r600_pipe_fences		fences;
+
+	unsigned			num_contexts;
+
+	/* for thread-safe write accessing to num_contexts */
+	pipe_mutex			mutex_num_contexts;
+};
+
+struct si_pipe_sampler_view {
+	struct pipe_sampler_view	base;
+	uint32_t			state[8];
+};
+
+struct si_pipe_sampler_state {
+	uint32_t			val[4];
+};
+
+struct r600_pipe_rasterizer {
+	struct r600_pipe_state		rstate;
+	boolean				flatshade;
+	unsigned			sprite_coord_enable;
+	unsigned			pa_sc_line_stipple;
+	unsigned			pa_su_sc_mode_cntl;
+	unsigned			pa_cl_clip_cntl;
+	unsigned			pa_cl_vs_out_cntl;
+	float				offset_units;
+	float				offset_scale;
+};
+
+struct r600_pipe_blend {
+	struct r600_pipe_state		rstate;
+	unsigned			cb_target_mask;
+	unsigned			cb_color_control;
+};
+
+struct r600_pipe_dsa {
+	struct r600_pipe_state		rstate;
+	unsigned			alpha_ref;
+	unsigned			db_render_override;
+	unsigned			db_render_control;
+	ubyte				valuemask[2];
+	ubyte				writemask[2];
+};
+
+struct r600_vertex_element
+{
+	unsigned			count;
+	struct pipe_vertex_element	elements[PIPE_MAX_ATTRIBS];
+	struct u_vbuf_elements		*vmgr_elements;
+	unsigned			fs_size;
+	struct r600_pipe_state		rstate;
+	/* if offset is to big for fetch instructio we need to alterate
+	 * offset of vertex buffer, record here the offset need to add
+	 */
+	unsigned			vbuffer_need_offset;
+	unsigned			vbuffer_offset[PIPE_MAX_ATTRIBS];
+};
+
+struct r600_shader_io {
+	unsigned		name;
+	unsigned		gpr;
+	unsigned		done;
+	int			sid;
+	unsigned		interpolate;
+	boolean                 centroid;
+	unsigned		lds_pos; /* for evergreen */
+};
+
+struct r600_shader {
+	unsigned		ninput;
+	unsigned		noutput;
+	struct r600_shader_io	input[32];
+	struct r600_shader_io	output[32];
+	boolean			uses_kill;
+	boolean			fs_write_all;
+	unsigned		nr_cbufs;
+};
+
+struct si_pipe_shader {
+	struct r600_shader		shader;
+	struct r600_pipe_state		rstate;
+	struct r600_resource		*bo;
+	struct r600_vertex_element	vertex_elements;
+	struct tgsi_token		*tokens;
+	unsigned			num_sgprs;
+	unsigned			num_vgprs;
+	unsigned			spi_ps_input_ena;
+	unsigned	sprite_coord_enable;
+	struct pipe_stream_output_info	so;
+	unsigned			so_strides[4];
+};
+
+/* needed for blitter save */
+#define NUM_TEX_UNITS 16
+
+struct r600_textures_info {
+	struct r600_pipe_state		rstate;
+	struct si_pipe_sampler_view	*views[NUM_TEX_UNITS];
+	struct si_pipe_sampler_state	*samplers[NUM_TEX_UNITS];
+	unsigned			n_views;
+	unsigned			n_samplers;
+	bool				samplers_dirty;
+	bool				is_array_sampler[NUM_TEX_UNITS];
+};
+
+struct r600_fence {
+	struct pipe_reference		reference;
+	unsigned			index; /* in the shared bo */
+	struct r600_resource            *sleep_bo;
+	struct list_head		head;
+};
+
+#define FENCE_BLOCK_SIZE 16
+
+struct r600_fence_block {
+	struct r600_fence		fences[FENCE_BLOCK_SIZE];
+	struct list_head		head;
+};
+
+#define R600_CONSTANT_ARRAY_SIZE 256
+#define R600_RESOURCE_ARRAY_SIZE 160
+
+struct r600_stencil_ref
+{
+	ubyte ref_value[2];
+	ubyte valuemask[2];
+	ubyte writemask[2];
+};
+
+struct r600_context {
+	struct pipe_context		context;
+	struct blitter_context		*blitter;
+	enum radeon_family		family;
+	enum chip_class			chip_class;
+	void				*custom_dsa_flush;
+	struct r600_screen		*screen;
+	struct radeon_winsys		*ws;
+	struct r600_pipe_state		*states[R600_PIPE_NSTATES];
+	struct r600_vertex_element	*vertex_elements;
+	struct pipe_framebuffer_state	framebuffer;
+	unsigned			cb_target_mask;
+	unsigned			cb_color_control;
+	unsigned			pa_sc_line_stipple;
+	unsigned			pa_su_sc_mode_cntl;
+	unsigned			pa_cl_clip_cntl;
+	unsigned			pa_cl_vs_out_cntl;
+	/* for saving when using blitter */
+	struct pipe_stencil_ref		stencil_ref;
+	struct pipe_viewport_state	viewport;
+	struct pipe_clip_state		clip;
+	struct r600_pipe_state		config;
+	struct si_pipe_shader 	*ps_shader;
+	struct si_pipe_shader 	*vs_shader;
+	struct r600_pipe_state		vs_const_buffer;
+	struct r600_pipe_state		vs_user_data;
+	struct r600_pipe_state		ps_const_buffer;
+	struct r600_pipe_rasterizer	*rasterizer;
+	struct r600_pipe_state          vgt;
+	struct r600_pipe_state          spi;
+	struct pipe_query		*current_render_cond;
+	unsigned			current_render_cond_mode;
+	struct pipe_query		*saved_render_cond;
+	unsigned			saved_render_cond_mode;
+	/* shader information */
+	unsigned			sprite_coord_enable;
+	boolean				export_16bpc;
+	unsigned			alpha_ref;
+	boolean				alpha_ref_dirty;
+	unsigned			nr_cbufs;
+	struct r600_textures_info	vs_samplers;
+	struct r600_textures_info	ps_samplers;
+	boolean				shader_dirty;
+
+	struct u_vbuf			*vbuf_mgr;
+	struct util_slab_mempool	pool_transfers;
+	boolean				have_depth_texture, have_depth_fb;
+
+	unsigned default_ps_gprs, default_vs_gprs;
+
+	/* States based on r600_state. */
+	struct list_head		dirty_states;
+	struct r600_atom_surface_sync	atom_surface_sync;
+	struct r600_atom		atom_r6xx_flush_and_inv;
+
+	/* Below are variables from the old r600_context.
+	 */
+	struct radeon_winsys_cs	*cs;
+
+	struct r600_range	*range;
+	unsigned		nblocks;
+	struct r600_block	**blocks;
+	struct list_head	dirty;
+	struct list_head	enable_list;
+	unsigned		pm4_dirty_cdwords;
+	unsigned		ctx_pm4_ndwords;
+	unsigned		init_dwords;
+
+	/* The list of active queries. Only one query of each type can be active. */
+	struct list_head	active_query_list;
+	unsigned		num_cs_dw_queries_suspend;
+	unsigned		num_cs_dw_streamout_end;
+
+	unsigned		backend_mask;
+	unsigned                max_db; /* for OQ */
+	unsigned		flags;
+	boolean                 predicate_drawing;
+
+	unsigned		num_so_targets;
+	struct r600_so_target	*so_targets[PIPE_MAX_SO_BUFFERS];
+	boolean			streamout_start;
+	unsigned		streamout_append_bitmask;
+	unsigned		*vs_so_stride_in_dw;
+	unsigned		*vs_shader_so_strides;
+};
+
+static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
+{
+	atom->emit(rctx, atom);
+	atom->dirty = false;
+	if (atom->head.next && atom->head.prev)
+		LIST_DELINIT(&atom->head);
+}
+
+static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
+{
+	if (!state->dirty) {
+		if (state->flags & EMIT_EARLY) {
+			LIST_ADD(&state->head, &rctx->dirty_states);
+		} else {
+			LIST_ADDTAIL(&state->head, &rctx->dirty_states);
+		}
+		state->dirty = true;
+	}
+}
+
+/* evergreen_state.c */
+void cayman_init_state_functions(struct r600_context *rctx);
+void si_init_config(struct r600_context *rctx);
+void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader);
+void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader);
+void si_update_spi_map(struct r600_context *rctx);
+void *cayman_create_db_flush_dsa(struct r600_context *rctx);
+void cayman_polygon_offset_update(struct r600_context *rctx);
+uint32_t si_translate_vertexformat(struct pipe_screen *screen,
+				   enum pipe_format format,
+				   const struct util_format_description *desc,
+				   int first_non_void);
+boolean si_is_format_supported(struct pipe_screen *screen,
+			       enum pipe_format format,
+			       enum pipe_texture_target target,
+			       unsigned sample_count,
+			       unsigned usage);
+
+/* r600_blit.c */
+void r600_init_blit_functions(struct r600_context *rctx);
+void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
+void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
+void r600_flush_depth_textures(struct r600_context *rctx);
+
+/* r600_buffer.c */
+bool r600_init_resource(struct r600_screen *rscreen,
+			struct r600_resource *res,
+			unsigned size, unsigned alignment,
+			unsigned bind, unsigned usage);
+struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
+					 const struct pipe_resource *templ);
+struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
+					      void *ptr, unsigned bytes,
+					      unsigned bind);
+void r600_upload_index_buffer(struct r600_context *rctx,
+			      struct pipe_index_buffer *ib, unsigned count);
+
+
+/* r600_pipe.c */
+void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
+		    unsigned flags);
+
+/* r600_query.c */
+void r600_init_query_functions(struct r600_context *rctx);
+
+/* r600_resource.c */
+void r600_init_context_resource_functions(struct r600_context *r600);
+
+/* radeonsi_shader.c */
+int si_pipe_shader_create(struct pipe_context *ctx, struct si_pipe_shader *shader);
+void si_pipe_shader_destroy(struct pipe_context *ctx, struct si_pipe_shader *shader);
+
+/* r600_texture.c */
+void r600_init_screen_texture_functions(struct pipe_screen *screen);
+void r600_init_surface_functions(struct r600_context *r600);
+unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
+					unsigned level, unsigned layer);
+
+/* r600_translate.c */
+void r600_translate_index_buffer(struct r600_context *r600,
+				 struct pipe_index_buffer *ib,
+				 unsigned count);
+
+/* r600_state_common.c */
+void r600_init_common_atoms(struct r600_context *rctx);
+unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
+void r600_texture_barrier(struct pipe_context *ctx);
+void r600_set_index_buffer(struct pipe_context *ctx,
+			   const struct pipe_index_buffer *ib);
+void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
+			     const struct pipe_vertex_buffer *buffers);
+void *si_create_vertex_elements(struct pipe_context *ctx,
+				unsigned count,
+				const struct pipe_vertex_element *elements);
+void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
+void r600_bind_blend_state(struct pipe_context *ctx, void *state);
+void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
+void r600_bind_rs_state(struct pipe_context *ctx, void *state);
+void r600_delete_rs_state(struct pipe_context *ctx, void *state);
+void r600_sampler_view_destroy(struct pipe_context *ctx,
+			       struct pipe_sampler_view *state);
+void r600_delete_state(struct pipe_context *ctx, void *state);
+void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
+void *si_create_shader_state(struct pipe_context *ctx,
+			     const struct pipe_shader_state *state);
+void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
+void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
+void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
+void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
+void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
+			      struct pipe_resource *buffer);
+struct pipe_stream_output_target *
+r600_create_so_target(struct pipe_context *ctx,
+		      struct pipe_resource *buffer,
+		      unsigned buffer_offset,
+		      unsigned buffer_size);
+void r600_so_target_destroy(struct pipe_context *ctx,
+			    struct pipe_stream_output_target *target);
+void r600_set_so_targets(struct pipe_context *ctx,
+			 unsigned num_targets,
+			 struct pipe_stream_output_target **targets,
+			 unsigned append_bitmask);
+void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
+			       const struct pipe_stencil_ref *state);
+void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
+
+/*
+ * common helpers
+ */
+static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
+{
+	return value * (1 << frac_bits);
+}
+#define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
+
+static inline unsigned r600_tex_aniso_filter(unsigned filter)
+{
+	if (filter <= 1)   return 0;
+	if (filter <= 2)   return 1;
+	if (filter <= 4)   return 2;
+	if (filter <= 8)   return 3;
+	 /* else */        return 4;
+}
+
+/* 12.4 fixed-point */
+static INLINE unsigned r600_pack_float_12p4(float x)
+{
+	return x <= 0    ? 0 :
+	       x >= 4096 ? 0xffff : x * 16;
+}
+
+static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
+{
+	struct r600_screen *rscreen = (struct r600_screen*)screen;
+	struct r600_resource *rresource = (struct r600_resource*)resource;
+
+	return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
+}
+
+#endif