radeonsi: initial WIP SI code

This commit adds initial support for acceleration
on SI chips.  egltri is starting to work.

The SI/R600 llvm backend is currently included in mesa
but that may change in the future.

The plan is to write a single gallium driver and
use gallium to support X acceleration.

This commit contains patches from:
Tom Stellard <[email protected]>
Michel Dänzer <[email protected]>
Alex Deucher <[email protected]>
Vadim Girlin <[email protected]>

Signed-off-by: Alex Deucher <[email protected]>

The following commits were squashed in:

======================================================================

radeonsi: Remove unused winsys pointer

This was removed from r600g in commit:

commit 96d882939d612fcc8332f107befec470ed4359de
Author: Marek Olšák <[email protected]>
Date:   Fri Feb 17 01:49:49 2012 +0100

    gallium: remove unused winsys pointers in pipe_screen and pipe_context

    A winsys is already a private object of a driver.

======================================================================

radeonsi: Copy color clamping CAPs from r600

Not sure if the values of these CAPS are correct for radeonsi, but the
same changed were made to r600g in commit:

commit bc1c8369384b5e16547c5bf9728aa78f8dfd66cc
Author: Marek Olšák <[email protected]>
Date:   Mon Jan 23 03:11:17 2012 +0100

    st/mesa: do vertex and fragment color clamping in shaders

    For ARB_color_buffer_float. Most hardware can't do it and st/mesa is
    the perfect place for a fallback.
    The exceptions are:
    - r500 (vertex clamp only)
    - nv50 (both)
    - nvc0 (both)
    - softpipe (both)

    We also have to take into account that r300 can do CLAMPED vertex colors only,
    while r600 can do UNCLAMPED vertex colors only. The difference can be expressed
    with the two new CAPs.

======================================================================

radeonsi: Remove PIPE_CAP_OUTPUT_READ

This CAP was dropped in commit:

commit 04e324008759282728a95a1394bac2c4c2a1a3f9
Author: Marek Olšák <[email protected]>
Date:   Thu Feb 23 23:44:36 2012 +0100

    gallium: remove PIPE_SHADER_CAP_OUTPUT_READ

    r600g is the only driver which has made use of it. The reason the CAP was
    added was to fix some piglit tests when the GLSL pass lower_output_reads
    didn't exist.

    However, not removing output reads breaks the fallback for glClampColorARB,
    which assumes outputs are not readable. The fix would be non-trivial
    and my personal preference is to remove the CAP, considering that reading
    outputs is uncommon and that we can now use lower_output_reads to fix
    the issue that the CAP was supposed to workaround in the first place.

======================================================================

radeonsi: Add missing parameters to rws->buffer_get_tiling() call

This was changed in commit:

commit c0c979eebc076b95cc8d18a013ce2968fe6311ad
Author: Jerome Glisse <[email protected]>
Date:   Mon Jan 30 17:22:13 2012 -0500

    r600g: add support for common surface allocator for tiling v13

    Tiled surface have all kind of alignment constraint that needs to
    be met. Instead of having all this code duplicated btw ddx and
    mesa use common code in libdrm_radeon this also ensure that both
    ddx and mesa compute those alignment in the same way.

    v2 fix evergreen
    v3 fix compressed texture and workaround cube texture issue by
       disabling 2D array mode for cubemap (need to check if r7xx and
       newer are also affected by the issue)
    v4 fix texture array
    v5 fix evergreen and newer, split surface values computation from
       mipmap tree generation so that we can get them directly from the
       ddx
    v6 final fix to evergreen tile split value
    v7 fix mipmap offset to avoid to use random value, use color view
       depth view to address different layer as hardware is doing some
       magic rotation depending on the layer
    v8 fix COLOR_VIEW on r6xx for linear array mode, use COLOR_VIEW on
       evergreen, align bytes per pixel to a multiple of a dword
    v9 fix handling of stencil on evergreen, half fix for compressed
       texture
    v10 fix evergreen compressed texture proper support for stencil
        tile split. Fix stencil issue when array mode was clear by
        the kernel, always program stencil bo. On evergreen depth
        buffer bo need to be big enough to hold depth buffer + stencil
        buffer as even with stencil disabled things get written there.
    v11 rebase on top of mesa, fix pitch issue with 1d surface on evergreen,
        old ddx overestimate those. Fix linear case when pitch*height < 64.
        Fix r300g.
    v12 Fix linear case when pitch*height < 64 for old path, adapt to
        libdrm API change
    v13 add libdrm check

    Signed-off-by: Jerome Glisse <[email protected]>

======================================================================

radeonsi: Remove PIPE_TRANSFER_MAP_PERMANENTLY

This was removed in commit:

commit 62f44f670bb0162e89fd4786af877f8da9ff607c
Author: Marek Olšák <[email protected]>
Date:   Mon Mar 5 13:45:00 2012 +0100

    Revert "gallium: add flag PIPE_TRANSFER_MAP_PERMANENTLY"

    This reverts commit 0950086376b1c8b7fb89eda81ed7f2f06dee58bc.

    It was decided to refactor the transfer API instead of adding workarounds
    to address the performance issues.

======================================================================

radeonsi: Handle PIPE_VIDEO_CAP_PREFERED_FORMAT.

Reintroduced in commit 9d9afcb5bac2931d4b8e6d1aa571e941c5110c90.

======================================================================

radeonsi: nuke the fallback for vertex and fragment color clamping

Ported from r600g commit c2b800cf38b299c1ab1c53dc0e4ea00c7acef853.

======================================================================

radeonsi: don't expose transform_feedback2 without kernel support

Ported from r600g commit 15146fd1bcbb08e44a1cbb984440ee1a5de63d48.

======================================================================

radeonsi: Handle PIPE_CAP_GLSL_FEATURE_LEVEL.

Ported from r600g part of commit 171be755223d99f8cc5cc1bdaf8bd7b4caa04b4f.

======================================================================

radeonsi: set minimum point size to 1.0 for non-sprite non-aa points.

Ported from r600g commit f183cc9ce3ad1d043bdf8b38fd519e8f437714fc.

======================================================================

radeonsi: rework and consolidate stencilref state setting.

Ported from r600g commit a2361946e782b57f0c63587841ca41c0ea707070.

======================================================================

radeonsi: cleanup setting DB_SHADER_CONTROL.

Ported from r600g commit 3d061caaed13b646ff40754f8ebe73f3d4983c5b.

======================================================================

radeonsi: Get rid of register masks.

Ported from r600g commits
3d061caaed13b646ff40754f8ebe73f3d4983c5b..9344ab382a1765c1a7c2560e771485edf4954fe2.

======================================================================

radeonsi: get rid of r600_context_reg.

Ported from r600g commits
9344ab382a1765c1a7c2560e771485edf4954fe2..bed20f02a771f43e1c5092254705701c228cfa7f.

======================================================================

radeonsi: Fix regression from 'Get rid of register masks'.

======================================================================

radeonsi: optimize r600_resource_va.

Ported from r600g commit 669d8766ff3403938794eb80d7769347b6e52174.

======================================================================

radeonsi: remove u8,u16,u32,u64 types.

Ported from r600g commit 78293b99b23268e6698f1267aaf40647c17d95a5.

======================================================================

radeonsi: merge r600_context with r600_pipe_context.

Ported from r600g commit e4340c1908a6a3b09e1a15d5195f6da7d00494d0.

======================================================================

radeonsi: Miscellaneous context cleanups.

Ported from r600g commits
e4340c1908a6a3b09e1a15d5195f6da7d00494d0..621e0db71c5ddcb379171064a4f720c9cf01e888.

======================================================================

radeonsi: add a new simple API for state emission.

Ported from r600g commits
621e0db71c5ddcb379171064a4f720c9cf01e888..f661405637bba32c2cfbeecf6e2e56e414e9521e.

======================================================================

radeonsi: Also remove sbu_flags member of struct r600_reg.

Requires using sid.h instead of r600d.h for the new CP_COHER_CNTL definitions,
so some code needs to be disabled for now.

======================================================================

radeonsi: Miscellaneous simplifications.

Ported from r600g commits 38bf2763482b4f1b6d95cd51aecec75601d8b90f and
b0337b679ad4c2feae59215104cfa60b58a619d5.

======================================================================

radeonsi: Handle PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION.

Ported from commit 8b4f7b0672d663273310fffa9490ad996f5b914a.

======================================================================

radeonsi: Use a fake reloc to sleep for fences.

Ported from r600g commit 8cd03b933cf868ff867e2db4a0937005a02fd0e4.

======================================================================

radeonsi: adapt to get_query_result interface change.

Ported from r600g commit 4445e170bee23a3607ece0e010adef7058ac6a11.

1 files changed, 731 insertions, 0 deletions

diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
new file mode 100644
index 00000000000..9e849525cc9
--- /dev/null
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
@@ -0,0 +1,731 @@
+/*
+ * Copyright 2010 Jerome Glisse <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * on the rights to use, copy, modify, merge, publish, distribute, sub
+ * license, and/or sell copies of the Software, and to permit persons to whom
+ * the Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include <stdio.h>
+#include <errno.h>
+#include "pipe/p_defines.h"
+#include "pipe/p_state.h"
+#include "pipe/p_context.h"
+#include "tgsi/tgsi_scan.h"
+#include "tgsi/tgsi_parse.h"
+#include "tgsi/tgsi_util.h"
+#include "util/u_blitter.h"
+#include "util/u_double_list.h"
+#include "util/u_format.h"
+#include "util/u_format_s3tc.h"
+#include "util/u_transfer.h"
+#include "util/u_surface.h"
+#include "util/u_pack_color.h"
+#include "util/u_memory.h"
+#include "util/u_inlines.h"
+#include "util/u_upload_mgr.h"
+#include "vl/vl_decoder.h"
+#include "vl/vl_video_buffer.h"
+#include "os/os_time.h"
+#include "pipebuffer/pb_buffer.h"
+#include "r600.h"
+#include "sid.h"
+#include "r600_resource.h"
+#include "radeonsi_pipe.h"
+#include "r600_hw_context_priv.h"
+
+/*
+ * pipe_context
+ */
+static struct r600_fence *r600_create_fence(struct r600_context *rctx)
+{
+	struct r600_screen *rscreen = rctx->screen;
+	struct r600_fence *fence = NULL;
+
+	pipe_mutex_lock(rscreen->fences.mutex);
+
+	if (!rscreen->fences.bo) {
+		/* Create the shared buffer object */
+		rscreen->fences.bo = (struct r600_resource*)
+			pipe_buffer_create(&rscreen->screen, PIPE_BIND_CUSTOM,
+					   PIPE_USAGE_STAGING, 4096);
+		if (!rscreen->fences.bo) {
+			R600_ERR("r600: failed to create bo for fence objects\n");
+			goto out;
+		}
+		rscreen->fences.data = rctx->ws->buffer_map(rscreen->fences.bo->buf,
+							   rctx->cs,
+							   PIPE_TRANSFER_READ_WRITE);
+	}
+
+	if (!LIST_IS_EMPTY(&rscreen->fences.pool)) {
+		struct r600_fence *entry;
+
+		/* Try to find a freed fence that has been signalled */
+		LIST_FOR_EACH_ENTRY(entry, &rscreen->fences.pool, head) {
+			if (rscreen->fences.data[entry->index] != 0) {
+				LIST_DELINIT(&entry->head);
+				fence = entry;
+				break;
+			}
+		}
+	}
+
+	if (!fence) {
+		/* Allocate a new fence */
+		struct r600_fence_block *block;
+		unsigned index;
+
+		if ((rscreen->fences.next_index + 1) >= 1024) {
+			R600_ERR("r600: too many concurrent fences\n");
+			goto out;
+		}
+
+		index = rscreen->fences.next_index++;
+
+		if (!(index % FENCE_BLOCK_SIZE)) {
+			/* Allocate a new block */
+			block = CALLOC_STRUCT(r600_fence_block);
+			if (block == NULL)
+				goto out;
+
+			LIST_ADD(&block->head, &rscreen->fences.blocks);
+		} else {
+			block = LIST_ENTRY(struct r600_fence_block, rscreen->fences.blocks.next, head);
+		}
+
+		fence = &block->fences[index % FENCE_BLOCK_SIZE];
+		fence->index = index;
+	}
+
+	pipe_reference_init(&fence->reference, 1);
+
+	rscreen->fences.data[fence->index] = 0;
+	r600_context_emit_fence(rctx, rscreen->fences.bo, fence->index, 1);
+
+	/* Create a dummy BO so that fence_finish without a timeout can sleep waiting for completion */
+	fence->sleep_bo = (struct r600_resource*)
+			pipe_buffer_create(&rctx->screen->screen, PIPE_BIND_CUSTOM,
+					   PIPE_USAGE_STAGING, 1);
+	/* Add the fence as a dummy relocation. */
+	r600_context_bo_reloc(rctx, fence->sleep_bo, RADEON_USAGE_READWRITE);
+
+out:
+	pipe_mutex_unlock(rscreen->fences.mutex);
+	return fence;
+}
+
+
+void radeonsi_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
+		    unsigned flags)
+{
+	struct r600_context *rctx = (struct r600_context *)ctx;
+	struct r600_fence **rfence = (struct r600_fence**)fence;
+	struct pipe_query *render_cond = NULL;
+	unsigned render_cond_mode = 0;
+
+	if (rfence)
+		*rfence = r600_create_fence(rctx);
+
+	/* Disable render condition. */
+	if (rctx->current_render_cond) {
+		render_cond = rctx->current_render_cond;
+		render_cond_mode = rctx->current_render_cond_mode;
+		ctx->render_condition(ctx, NULL, 0);
+	}
+
+	r600_context_flush(rctx, flags);
+
+	/* Re-enable render condition. */
+	if (render_cond) {
+		ctx->render_condition(ctx, render_cond, render_cond_mode);
+	}
+}
+
+static void r600_flush_from_st(struct pipe_context *ctx,
+			       struct pipe_fence_handle **fence)
+{
+	radeonsi_flush(ctx, fence, 0);
+}
+
+static void r600_flush_from_winsys(void *ctx, unsigned flags)
+{
+	radeonsi_flush((struct pipe_context*)ctx, NULL, flags);
+}
+
+static void r600_update_num_contexts(struct r600_screen *rscreen, int diff)
+{
+	pipe_mutex_lock(rscreen->mutex_num_contexts);
+	if (diff > 0) {
+		rscreen->num_contexts++;
+
+		if (rscreen->num_contexts > 1)
+			util_slab_set_thread_safety(&rscreen->pool_buffers,
+						    UTIL_SLAB_MULTITHREADED);
+	} else {
+		rscreen->num_contexts--;
+
+		if (rscreen->num_contexts <= 1)
+			util_slab_set_thread_safety(&rscreen->pool_buffers,
+						    UTIL_SLAB_SINGLETHREADED);
+	}
+	pipe_mutex_unlock(rscreen->mutex_num_contexts);
+}
+
+static void r600_destroy_context(struct pipe_context *context)
+{
+	struct r600_context *rctx = (struct r600_context *)context;
+
+	rctx->context.delete_depth_stencil_alpha_state(&rctx->context, rctx->custom_dsa_flush);
+	util_unreference_framebuffer_state(&rctx->framebuffer);
+
+	r600_context_fini(rctx);
+
+	util_blitter_destroy(rctx->blitter);
+
+	for (int i = 0; i < R600_PIPE_NSTATES; i++) {
+		free(rctx->states[i]);
+	}
+
+	u_vbuf_destroy(rctx->vbuf_mgr);
+	util_slab_destroy(&rctx->pool_transfers);
+
+	r600_update_num_contexts(rctx->screen, -1);
+
+	FREE(rctx);
+}
+
+static struct pipe_context *r600_create_context(struct pipe_screen *screen, void *priv)
+{
+	struct r600_context *rctx = CALLOC_STRUCT(r600_context);
+	struct r600_screen* rscreen = (struct r600_screen *)screen;
+
+	if (rctx == NULL)
+		return NULL;
+
+	r600_update_num_contexts(rscreen, 1);
+
+	rctx->context.screen = screen;
+	rctx->context.priv = priv;
+	rctx->context.destroy = r600_destroy_context;
+	rctx->context.flush = r600_flush_from_st;
+
+	/* Easy accessing of screen/winsys. */
+	rctx->screen = rscreen;
+	rctx->ws = rscreen->ws;
+	rctx->family = rscreen->family;
+	rctx->chip_class = rscreen->chip_class;
+
+	r600_init_blit_functions(rctx);
+	r600_init_query_functions(rctx);
+	r600_init_context_resource_functions(rctx);
+	r600_init_surface_functions(rctx);
+	rctx->context.draw_vbo = r600_draw_vbo;
+
+	rctx->context.create_video_decoder = vl_create_decoder;
+	rctx->context.create_video_buffer = vl_video_buffer_create;
+
+	r600_init_common_atoms(rctx);
+
+	switch (rctx->chip_class) {
+	case TAHITI:
+		cayman_init_state_functions(rctx);
+		if (si_context_init(rctx)) {
+			r600_destroy_context(&rctx->context);
+			return NULL;
+		}
+		si_init_config(rctx);
+		rctx->custom_dsa_flush = cayman_create_db_flush_dsa(rctx);
+		break;
+	default:
+		R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
+		r600_destroy_context(&rctx->context);
+		return NULL;
+	}
+
+	rctx->ws->cs_set_flush_callback(rctx->cs, r600_flush_from_winsys, rctx);
+
+	util_slab_create(&rctx->pool_transfers,
+			 sizeof(struct pipe_transfer), 64,
+			 UTIL_SLAB_SINGLETHREADED);
+
+	rctx->vbuf_mgr = u_vbuf_create(&rctx->context, 1024 * 1024, 256,
+					   PIPE_BIND_VERTEX_BUFFER |
+					   PIPE_BIND_INDEX_BUFFER |
+					   PIPE_BIND_CONSTANT_BUFFER,
+					   U_VERTEX_FETCH_DWORD_ALIGNED);
+	if (!rctx->vbuf_mgr) {
+		r600_destroy_context(&rctx->context);
+		return NULL;
+	}
+	rctx->vbuf_mgr->caps.format_fixed32 = 0;
+
+	rctx->blitter = util_blitter_create(&rctx->context);
+	if (rctx->blitter == NULL) {
+		r600_destroy_context(&rctx->context);
+		return NULL;
+	}
+
+	LIST_INITHEAD(&rctx->dirty_states);
+
+	r600_get_backend_mask(rctx); /* this emits commands and must be last */
+
+	return &rctx->context;
+}
+
+/*
+ * pipe_screen
+ */
+static const char* r600_get_vendor(struct pipe_screen* pscreen)
+{
+	return "X.Org";
+}
+
+static const char *r600_get_family_name(enum radeon_family family)
+{
+	switch(family) {
+	case CHIP_CAYMAN: return "AMD CAYMAN";
+	default: return "AMD unknown";
+	}
+}
+
+static const char* r600_get_name(struct pipe_screen* pscreen)
+{
+	struct r600_screen *rscreen = (struct r600_screen *)pscreen;
+
+	return r600_get_family_name(rscreen->family);
+}
+
+static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
+{
+	struct r600_screen *rscreen = (struct r600_screen *)pscreen;
+	enum radeon_family family = rscreen->family;
+
+	switch (param) {
+	/* Supported features (boolean caps). */
+	case PIPE_CAP_NPOT_TEXTURES:
+	case PIPE_CAP_TWO_SIDED_STENCIL:
+	case PIPE_CAP_DUAL_SOURCE_BLEND:
+	case PIPE_CAP_ANISOTROPIC_FILTER:
+	case PIPE_CAP_POINT_SPRITE:
+	case PIPE_CAP_OCCLUSION_QUERY:
+	case PIPE_CAP_TEXTURE_SHADOW_MAP:
+	case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
+	case PIPE_CAP_BLEND_EQUATION_SEPARATE:
+	case PIPE_CAP_TEXTURE_SWIZZLE:
+	case PIPE_CAP_DEPTHSTENCIL_CLEAR_SEPARATE:
+	case PIPE_CAP_DEPTH_CLIP_DISABLE:
+	case PIPE_CAP_SHADER_STENCIL_EXPORT:
+	case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
+	case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
+	case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
+	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
+	case PIPE_CAP_SM3:
+	case PIPE_CAP_SEAMLESS_CUBE_MAP:
+	case PIPE_CAP_PRIMITIVE_RESTART:
+	case PIPE_CAP_CONDITIONAL_RENDER:
+	case PIPE_CAP_TEXTURE_BARRIER:
+	case PIPE_CAP_INDEP_BLEND_ENABLE:
+	case PIPE_CAP_INDEP_BLEND_FUNC:
+	case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
+	case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
+		return 1;
+
+	case PIPE_CAP_GLSL_FEATURE_LEVEL:
+		return debug_get_bool_option("R600_GLSL130", FALSE) ? 130 : 120;
+
+	/* Unsupported features. */
+	case PIPE_CAP_TGSI_INSTANCEID:
+	case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
+	case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
+	case PIPE_CAP_SCALED_RESOLVE:
+	case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
+	case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
+	case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
+	case PIPE_CAP_VERTEX_COLOR_CLAMPED:
+	case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
+		return 0;
+
+	/* Stream output. */
+	case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
+		return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 4 : 0;
+	case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
+		return debug_get_bool_option("R600_STREAMOUT", FALSE) ? 1 : 0;
+	case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
+	case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
+		return 16*4;
+
+	/* Texturing. */
+	case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
+	case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
+	case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
+			return 15;
+	case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
+		return rscreen->info.drm_minor >= 9 ? 16384 : 0;
+	case PIPE_CAP_MAX_COMBINED_SAMPLERS:
+		return 32;
+
+	/* Render targets. */
+	case PIPE_CAP_MAX_RENDER_TARGETS:
+		/* FIXME some r6xx are buggy and can only do 4 */
+		return 8;
+
+	/* Timer queries, present when the clock frequency is non zero. */
+	case PIPE_CAP_TIMER_QUERY:
+		return rscreen->info.r600_clock_crystal_freq != 0;
+
+	case PIPE_CAP_MIN_TEXEL_OFFSET:
+		return -8;
+
+	case PIPE_CAP_MAX_TEXEL_OFFSET:
+		return 7;
+	}
+	return 0;
+}
+
+static float r600_get_paramf(struct pipe_screen* pscreen,
+			     enum pipe_capf param)
+{
+	struct r600_screen *rscreen = (struct r600_screen *)pscreen;
+	enum radeon_family family = rscreen->family;
+
+	switch (param) {
+	case PIPE_CAPF_MAX_LINE_WIDTH:
+	case PIPE_CAPF_MAX_LINE_WIDTH_AA:
+	case PIPE_CAPF_MAX_POINT_WIDTH:
+	case PIPE_CAPF_MAX_POINT_WIDTH_AA:
+		return 16384.0f;
+	case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
+		return 16.0f;
+	case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
+		return 16.0f;
+	case PIPE_CAPF_GUARD_BAND_LEFT:
+	case PIPE_CAPF_GUARD_BAND_TOP:
+	case PIPE_CAPF_GUARD_BAND_RIGHT:
+	case PIPE_CAPF_GUARD_BAND_BOTTOM:
+		return 0.0f;
+	}
+	return 0.0f;
+}
+
+static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
+{
+	struct r600_screen *rscreen = (struct r600_screen *)pscreen;
+	switch(shader)
+	{
+	case PIPE_SHADER_FRAGMENT:
+	case PIPE_SHADER_VERTEX:
+		break;
+	case PIPE_SHADER_GEOMETRY:
+		/* TODO: support and enable geometry programs */
+		return 0;
+	default:
+		/* TODO: support tessellation */
+		return 0;
+	}
+
+	/* TODO: all these should be fixed, since r600 surely supports much more! */
+	switch (param) {
+	case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
+	case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
+	case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
+	case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
+		return 16384;
+	case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
+		return 8; /* FIXME */
+	case PIPE_SHADER_CAP_MAX_INPUTS:
+		if(shader == PIPE_SHADER_FRAGMENT)
+			return 34;
+		else
+			return 32;
+	case PIPE_SHADER_CAP_MAX_TEMPS:
+		return 256; /* Max native temporaries. */
+	case PIPE_SHADER_CAP_MAX_ADDRS:
+		/* FIXME Isn't this equal to TEMPS? */
+		return 1; /* Max native address registers */
+	case PIPE_SHADER_CAP_MAX_CONSTS:
+		return R600_MAX_CONST_BUFFER_SIZE;
+	case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
+		return R600_MAX_CONST_BUFFERS;
+	case PIPE_SHADER_CAP_MAX_PREDS:
+		return 0; /* FIXME */
+	case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
+		return 1;
+	case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
+	case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
+	case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
+	case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
+	case PIPE_SHADER_CAP_INTEGERS:
+		return 0;
+	case PIPE_SHADER_CAP_SUBROUTINES:
+		return 0;
+	case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
+		return 16;
+	}
+	return 0;
+}
+
+static int r600_get_video_param(struct pipe_screen *screen,
+				enum pipe_video_profile profile,
+				enum pipe_video_cap param)
+{
+	switch (param) {
+	case PIPE_VIDEO_CAP_SUPPORTED:
+		return vl_profile_supported(screen, profile);
+	case PIPE_VIDEO_CAP_NPOT_TEXTURES:
+		return 1;
+	case PIPE_VIDEO_CAP_MAX_WIDTH:
+	case PIPE_VIDEO_CAP_MAX_HEIGHT:
+		return vl_video_buffer_max_size(screen);
+	case PIPE_VIDEO_CAP_PREFERED_FORMAT:
+		return PIPE_FORMAT_NV12;
+	default:
+		return 0;
+	}
+}
+
+static void r600_destroy_screen(struct pipe_screen* pscreen)
+{
+	struct r600_screen *rscreen = (struct r600_screen *)pscreen;
+
+	if (rscreen == NULL)
+		return;
+
+	if (rscreen->fences.bo) {
+		struct r600_fence_block *entry, *tmp;
+
+		LIST_FOR_EACH_ENTRY_SAFE(entry, tmp, &rscreen->fences.blocks, head) {
+			LIST_DEL(&entry->head);
+			FREE(entry);
+		}
+
+		rscreen->ws->buffer_unmap(rscreen->fences.bo->buf);
+		pipe_resource_reference((struct pipe_resource**)&rscreen->fences.bo, NULL);
+	}
+	pipe_mutex_destroy(rscreen->fences.mutex);
+
+	rscreen->ws->destroy(rscreen->ws);
+
+	util_slab_destroy(&rscreen->pool_buffers);
+	pipe_mutex_destroy(rscreen->mutex_num_contexts);
+	FREE(rscreen);
+}
+
+static void r600_fence_reference(struct pipe_screen *pscreen,
+                                 struct pipe_fence_handle **ptr,
+                                 struct pipe_fence_handle *fence)
+{
+	struct r600_fence **oldf = (struct r600_fence**)ptr;
+	struct r600_fence *newf = (struct r600_fence*)fence;
+
+	if (pipe_reference(&(*oldf)->reference, &newf->reference)) {
+		struct r600_screen *rscreen = (struct r600_screen *)pscreen;
+		pipe_mutex_lock(rscreen->fences.mutex);
+		pipe_resource_reference((struct pipe_resource**)&(*oldf)->sleep_bo, NULL);
+		LIST_ADDTAIL(&(*oldf)->head, &rscreen->fences.pool);
+		pipe_mutex_unlock(rscreen->fences.mutex);
+	}
+
+	*ptr = fence;
+}
+
+static boolean r600_fence_signalled(struct pipe_screen *pscreen,
+                                    struct pipe_fence_handle *fence)
+{
+	struct r600_screen *rscreen = (struct r600_screen *)pscreen;
+	struct r600_fence *rfence = (struct r600_fence*)fence;
+
+	return rscreen->fences.data[rfence->index];
+}
+
+static boolean r600_fence_finish(struct pipe_screen *pscreen,
+                                 struct pipe_fence_handle *fence,
+                                 uint64_t timeout)
+{
+	struct r600_screen *rscreen = (struct r600_screen *)pscreen;
+	struct r600_fence *rfence = (struct r600_fence*)fence;
+	int64_t start_time = 0;
+	unsigned spins = 0;
+
+	if (timeout != PIPE_TIMEOUT_INFINITE) {
+		start_time = os_time_get();
+
+		/* Convert to microseconds. */
+		timeout /= 1000;
+	}
+
+	while (rscreen->fences.data[rfence->index] == 0) {
+		/* Special-case infinite timeout - wait for the dummy BO to become idle */
+		if (timeout == PIPE_TIMEOUT_INFINITE) {
+			rscreen->ws->buffer_wait(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE);
+			break;
+		}
+
+		/* The dummy BO will be busy until the CS including the fence has completed, or
+		 * the GPU is reset. Don't bother continuing to spin when the BO is idle. */
+		if (!rscreen->ws->buffer_is_busy(rfence->sleep_bo->buf, RADEON_USAGE_READWRITE))
+			break;
+
+		if (++spins % 256)
+			continue;
+#ifdef PIPE_OS_UNIX
+		sched_yield();
+#else
+		os_time_sleep(10);
+#endif
+		if (timeout != PIPE_TIMEOUT_INFINITE &&
+		    os_time_get() - start_time >= timeout) {
+			break;
+		}
+	}
+
+	return rscreen->fences.data[rfence->index] != 0;
+}
+
+static int evergreen_interpret_tiling(struct r600_screen *rscreen, uint32_t tiling_config)
+{
+	switch (tiling_config & 0xf) {
+	case 0:
+		rscreen->tiling_info.num_channels = 1;
+		break;
+	case 1:
+		rscreen->tiling_info.num_channels = 2;
+		break;
+	case 2:
+		rscreen->tiling_info.num_channels = 4;
+		break;
+	case 3:
+		rscreen->tiling_info.num_channels = 8;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	switch ((tiling_config & 0xf0) >> 4) {
+	case 0:
+		rscreen->tiling_info.num_banks = 4;
+		break;
+	case 1:
+		rscreen->tiling_info.num_banks = 8;
+		break;
+	case 2:
+		rscreen->tiling_info.num_banks = 16;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	switch ((tiling_config & 0xf00) >> 8) {
+	case 0:
+		rscreen->tiling_info.group_bytes = 256;
+		break;
+	case 1:
+		rscreen->tiling_info.group_bytes = 512;
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int r600_init_tiling(struct r600_screen *rscreen)
+{
+	uint32_t tiling_config = rscreen->info.r600_tiling_config;
+
+	/* set default group bytes, overridden by tiling info ioctl */
+	rscreen->tiling_info.group_bytes = 512;
+
+	if (!tiling_config)
+		return 0;
+
+	return evergreen_interpret_tiling(rscreen, tiling_config);
+}
+
+static unsigned radeon_family_from_device(unsigned device)
+{
+	switch (device) {
+#define CHIPSET(pciid, name, family) case pciid: return CHIP_##family;
+#include "pci_ids/radeonsi_pci_ids.h"
+#undef CHIPSET
+	default:
+		return CHIP_UNKNOWN;
+	}
+}
+
+struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
+{
+	struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
+	if (rscreen == NULL) {
+		return NULL;
+	}
+
+	rscreen->ws = ws;
+	ws->query_info(ws, &rscreen->info);
+
+	rscreen->family = radeon_family_from_device(rscreen->info.pci_id);
+	if (rscreen->family == CHIP_UNKNOWN) {
+		fprintf(stderr, "r600: Unknown chipset 0x%04X\n", rscreen->info.pci_id);
+		FREE(rscreen);
+		return NULL;
+	}
+
+	/* setup class */
+	if (rscreen->family >= CHIP_TAHITI) {
+		rscreen->chip_class = TAHITI;
+	} else {
+		fprintf(stderr, "r600: Unsupported family %d\n", rscreen->family);
+		FREE(rscreen);
+		return NULL;
+	}
+
+	if (r600_init_tiling(rscreen)) {
+		FREE(rscreen);
+		return NULL;
+	}
+
+	rscreen->screen.destroy = r600_destroy_screen;
+	rscreen->screen.get_name = r600_get_name;
+	rscreen->screen.get_vendor = r600_get_vendor;
+	rscreen->screen.get_param = r600_get_param;
+	rscreen->screen.get_shader_param = r600_get_shader_param;
+	rscreen->screen.get_paramf = r600_get_paramf;
+	rscreen->screen.get_video_param = r600_get_video_param;
+	rscreen->screen.is_format_supported = si_is_format_supported;
+	rscreen->screen.is_video_format_supported = vl_video_buffer_is_format_supported;
+	rscreen->screen.context_create = r600_create_context;
+	rscreen->screen.fence_reference = r600_fence_reference;
+	rscreen->screen.fence_signalled = r600_fence_signalled;
+	rscreen->screen.fence_finish = r600_fence_finish;
+	r600_init_screen_resource_functions(&rscreen->screen);
+
+	util_format_s3tc_init();
+
+	util_slab_create(&rscreen->pool_buffers,
+			 sizeof(struct r600_resource), 64,
+			 UTIL_SLAB_SINGLETHREADED);
+
+	pipe_mutex_init(rscreen->mutex_num_contexts);
+
+	rscreen->fences.bo = NULL;
+	rscreen->fences.data = NULL;
+	rscreen->fences.next_index = 0;
+	LIST_INITHEAD(&rscreen->fences.pool);
+	LIST_INITHEAD(&rscreen->fences.blocks);
+	pipe_mutex_init(rscreen->fences.mutex);
+
+	return &rscreen->screen;
+}