diff options
| author | Michel Dänzer <[email protected]> | 2013-01-17 16:31:58 +0100 |
|---|---|---|
| committer | Michel Dänzer <[email protected]> | 2013-01-17 16:57:20 +0100 |
| commit | c486e3ef342ea7bace4c124f905bfa154f47dacc (patch) | |
| tree | b2e2204df91f80ee66e50c753c12f556c8ed4dc8 /src/gallium/drivers/radeonsi/r600_texture.c | |
| parent | c408f0c5c4b07eac4bc8759bb8e6ab20f527ded0 (diff) | |
radeonsi: Enable tiling for depth/stencil resources.
Enabling it for all resources still seems to cause problems, but depth/stencil
buffers are always accessed with tiling by the DB block.
Also, stick to 1D tiling for now. Getting 2D tiling to work properly will
require substantial changes in libdrm_radeon and possibly the kernel as well.
Reviewed-by: Christian König <[email protected]>
Signed-off-by: Michel Dänzer <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/r600_texture.c')
| -rw-r--r-- | src/gallium/drivers/radeonsi/r600_texture.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/src/gallium/drivers/radeonsi/r600_texture.c b/src/gallium/drivers/radeonsi/r600_texture.c index de46640d7e4..580af540f74 100644 --- a/src/gallium/drivers/radeonsi/r600_texture.c +++ b/src/gallium/drivers/radeonsi/r600_texture.c @@ -521,14 +521,13 @@ struct pipe_resource *si_texture_create(struct pipe_screen *screen, unsigned array_mode = V_009910_ARRAY_LINEAR_ALIGNED; int r; -#if 0 if (!(templ->flags & R600_RESOURCE_FLAG_TRANSFER) && - !(templ->bind & PIPE_BIND_SCANOUT)) { + !(templ->bind & PIPE_BIND_SCANOUT) && + util_format_is_depth_or_stencil(templ->format)) { if (permit_hardware_blit(screen, templ)) { - array_mode = V_009910_ARRAY_2D_TILED_THIN1; + array_mode = V_009910_ARRAY_1D_TILED_THIN1; } } -#endif r = r600_init_surface(rscreen, &surface, templ, array_mode, templ->flags & R600_RESOURCE_FLAG_FLUSHED_DEPTH); |