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authorMichel Dänzer <[email protected]>2012-05-16 18:19:13 +0200
committerMichel Dänzer <[email protected]>2012-05-16 18:30:50 +0200
commit88a2e2388bfeee66cb6d873558431b0e0af7e316 (patch)
treeb0517d915ab8e72a320317c37f2e6b0c4fa2ef30 /src/gallium/drivers/radeonsi/r600_resource.h
parent11f056a3f0b87e86267efa8b5ac9d36a343c9dc1 (diff)
radeonsi: Initial tiling support.
Largely based on the corresponding Evergreen support in r600g.
Diffstat (limited to 'src/gallium/drivers/radeonsi/r600_resource.h')
-rw-r--r--src/gallium/drivers/radeonsi/r600_resource.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeonsi/r600_resource.h b/src/gallium/drivers/radeonsi/r600_resource.h
index 6926d764cbe..314fb239b83 100644
--- a/src/gallium/drivers/radeonsi/r600_resource.h
+++ b/src/gallium/drivers/radeonsi/r600_resource.h
@@ -53,15 +53,15 @@ struct r600_resource_texture {
unsigned array_mode[PIPE_MAX_TEXTURE_LEVELS];
unsigned pitch_override;
unsigned size;
- unsigned tile_type;
unsigned depth;
unsigned dirty_db;
struct r600_resource_texture *stencil; /* Stencil is in a separate buffer on Evergreen. */
struct r600_resource_texture *flushed_depth_texture;
boolean is_flushing_texture;
+ struct radeon_surface surface;
};
-#define R600_TEX_IS_TILED(tex, level) ((tex)->array_mode[level] != V_038000_ARRAY_LINEAR_GENERAL && (tex)->array_mode[level] != V_038000_ARRAY_LINEAR_ALIGNED)
+#define R600_TEX_IS_TILED(tex, level) ((tex)->array_mode[level] != V_009910_ARRAY_LINEAR_GENERAL && (tex)->array_mode[level] != V_009910_ARRAY_LINEAR_ALIGNED)
struct r600_surface {
struct pipe_surface base;