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authorChristian König <[email protected]>2012-07-18 14:36:10 +0200
committerChristian König <[email protected]>2012-07-24 12:29:30 +0200
commitbd2a5cf328c21f2d5b243442ee2eac73a996b15c (patch)
tree64e48ffc360f396f4ad29fea4bb76d000fb8ac31 /src/gallium/drivers/radeonsi/evergreen_state.c
parent840f05da6b92ba5266385836533842b9a9fc5da9 (diff)
radeonsi: move spi into new handling
Signed-off-by: Christian König <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/evergreen_state.c')
-rw-r--r--src/gallium/drivers/radeonsi/evergreen_state.c46
1 files changed, 0 insertions, 46 deletions
diff --git a/src/gallium/drivers/radeonsi/evergreen_state.c b/src/gallium/drivers/radeonsi/evergreen_state.c
index 1a6ffd81d47..b04c1cb9ecf 100644
--- a/src/gallium/drivers/radeonsi/evergreen_state.c
+++ b/src/gallium/drivers/radeonsi/evergreen_state.c
@@ -1288,50 +1288,4 @@ void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
NULL, 0);
}
-void si_update_spi_map(struct r600_context *rctx)
-{
- struct r600_shader *ps = &rctx->ps_shader->shader;
- struct r600_shader *vs = &rctx->vs_shader->shader;
- struct r600_pipe_state *rstate = &rctx->spi;
- unsigned i, j, tmp;
-
- rstate->nregs = 0;
-
- for (i = 0; i < ps->ninput; i++) {
- tmp = 0;
-
-#if 0
- /* XXX: Flat shading hangs the GPU */
- if (ps->input[i].name == TGSI_SEMANTIC_POSITION ||
- ps->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
- (ps->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
- rctx->rasterizer && rctx->rasterizer->flatshade)) {
- tmp |= S_028644_FLAT_SHADE(1);
- }
-#endif
-
- if (ps->input[i].name == TGSI_SEMANTIC_GENERIC &&
- rctx->sprite_coord_enable & (1 << ps->input[i].sid)) {
- tmp |= S_028644_PT_SPRITE_TEX(1);
- }
-
- for (j = 0; j < vs->noutput; j++) {
- if (ps->input[i].name == vs->output[j].name &&
- ps->input[i].sid == vs->output[j].sid) {
- tmp |= S_028644_OFFSET(vs->output[j].param_offset);
- break;
- }
- }
- if (j == vs->noutput) {
- /* No corresponding output found, load defaults into input */
- tmp |= S_028644_OFFSET(0x20);
- }
-
- r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
- tmp, NULL, 0);
- }
-
- if (rstate->nregs > 0)
- r600_context_pipe_state_set(rctx, rstate);
-}