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authorNicolai Hähnle <[email protected]>2017-09-08 15:15:08 +0200
committerNicolai Hähnle <[email protected]>2017-09-18 11:25:19 +0200
commit8c56c45cd48e940283a8d3e951750c57694718f9 (patch)
tree16af1e409dd10d6c248d9392d5355b532fd58c49 /src/gallium/drivers/radeonsi/driinfo_radeonsi.h
parentaab134cfa57cd2f72d4234fe3f41e392e6a4f48d (diff)
radeonsi: add drirc option "radeonsi_assume_no_z_fights"
This option enables a performance optimization where typical non-blending draws with depth buffer may be rasterized out-of-order (on VI+, multi-SE chips). This optimization can lead to incorrect results when an applications renders multiple objects with the same Z value at the same pixel, so we will never enable it by default. But there may be applications that could benefit from white-listing. Reviewed-by: Marek Olšák <[email protected]> Tested-by: Dieter Nützel <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeonsi/driinfo_radeonsi.h')
-rw-r--r--src/gallium/drivers/radeonsi/driinfo_radeonsi.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/driinfo_radeonsi.h b/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
index af6284a7787..8be85289a0c 100644
--- a/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
+++ b/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
@@ -1,4 +1,5 @@
// DriConf options specific to radeonsi
DRI_CONF_SECTION_PERFORMANCE
DRI_CONF_RADEONSI_ENABLE_SISCHED("false")
+ DRI_CONF_RADEONSI_ASSUME_NO_Z_FIGHTS("false")
DRI_CONF_SECTION_END