gallium/radeon: move pre-GFX9 radeon_surf.* members to radeon_surf.u.legacy.*

Reviewed-by: Nicolai Hähnle <[email protected]>

1 files changed, 20 insertions, 20 deletions

diff --git a/src/gallium/drivers/radeonsi/cik_sdma.c b/src/gallium/drivers/radeonsi/cik_sdma.c
index 500afb07c0b..38833666a8d 100644
--- a/src/gallium/drivers/radeonsi/cik_sdma.c
+++ b/src/gallium/drivers/radeonsi/cik_sdma.c
@@ -120,8 +120,8 @@ static unsigned encode_tile_info(struct si_context *sctx,
 				 bool set_bpp)
 {
 	struct radeon_info *info = &sctx->screen->b.info;
-	unsigned tile_index = tex->surface.tiling_index[level];
-	unsigned macro_tile_index = tex->surface.macro_tile_index;
+	unsigned tile_index = tex->surface.u.legacy.tiling_index[level];
+	unsigned macro_tile_index = tex->surface.u.legacy.macro_tile_index;
 	unsigned tile_mode = info->si_tile_mode_array[tile_index];
 	unsigned macro_tile_mode = info->cik_macrotile_mode_array[macro_tile_index];
 
@@ -129,7 +129,7 @@ static unsigned encode_tile_info(struct si_context *sctx,
 		(G_009910_ARRAY_MODE(tile_mode) << 3) |
 		(G_009910_MICRO_TILE_MODE_NEW(tile_mode) << 8) |
 		/* Non-depth modes don't have TILE_SPLIT set. */
-		((util_logbase2(tex->surface.tile_split >> 6)) << 11) |
+		((util_logbase2(tex->surface.u.legacy.tile_split >> 6)) << 11) |
 		(G_009990_BANK_WIDTH(macro_tile_mode) << 15) |
 		(G_009990_BANK_HEIGHT(macro_tile_mode) << 18) |
 		(G_009990_NUM_BANKS(macro_tile_mode) << 21) |
@@ -150,21 +150,21 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
 	struct r600_texture *rdst = (struct r600_texture*)dst;
 	unsigned bpp = rdst->surface.bpe;
 	uint64_t dst_address = rdst->resource.gpu_address +
-			       rdst->surface.level[dst_level].offset;
+			       rdst->surface.u.legacy.level[dst_level].offset;
 	uint64_t src_address = rsrc->resource.gpu_address +
-			       rsrc->surface.level[src_level].offset;
-	unsigned dst_mode = rdst->surface.level[dst_level].mode;
-	unsigned src_mode = rsrc->surface.level[src_level].mode;
-	unsigned dst_tile_index = rdst->surface.tiling_index[dst_level];
-	unsigned src_tile_index = rsrc->surface.tiling_index[src_level];
+			       rsrc->surface.u.legacy.level[src_level].offset;
+	unsigned dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
+	unsigned src_mode = rsrc->surface.u.legacy.level[src_level].mode;
+	unsigned dst_tile_index = rdst->surface.u.legacy.tiling_index[dst_level];
+	unsigned src_tile_index = rsrc->surface.u.legacy.tiling_index[src_level];
 	unsigned dst_tile_mode = info->si_tile_mode_array[dst_tile_index];
 	unsigned src_tile_mode = info->si_tile_mode_array[src_tile_index];
 	unsigned dst_micro_mode = G_009910_MICRO_TILE_MODE_NEW(dst_tile_mode);
 	unsigned src_micro_mode = G_009910_MICRO_TILE_MODE_NEW(src_tile_mode);
-	unsigned dst_pitch = rdst->surface.level[dst_level].nblk_x;
-	unsigned src_pitch = rsrc->surface.level[src_level].nblk_x;
-	uint64_t dst_slice_pitch = rdst->surface.level[dst_level].slice_size / bpp;
-	uint64_t src_slice_pitch = rsrc->surface.level[src_level].slice_size / bpp;
+	unsigned dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x;
+	unsigned src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x;
+	uint64_t dst_slice_pitch = rdst->surface.u.legacy.level[dst_level].slice_size / bpp;
+	uint64_t src_slice_pitch = rsrc->surface.u.legacy.level[src_level].slice_size / bpp;
 	unsigned dst_width = minify_as_blocks(rdst->resource.b.b.width0,
 					      dst_level, rdst->surface.blk_w);
 	unsigned src_width = minify_as_blocks(rsrc->resource.b.b.width0,
@@ -182,10 +182,10 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
 
 	assert(src_level <= src->last_level);
 	assert(dst_level <= dst->last_level);
-	assert(rdst->surface.level[dst_level].offset +
+	assert(rdst->surface.u.legacy.level[dst_level].offset +
 	       dst_slice_pitch * bpp * (dstz + src_box->depth) <=
 	       rdst->resource.buf->size);
-	assert(rsrc->surface.level[src_level].offset +
+	assert(rsrc->surface.u.legacy.level[src_level].offset +
 	       src_slice_pitch * bpp * (srcz + src_box->depth) <=
 	       rsrc->resource.buf->size);
 
@@ -350,14 +350,14 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
 		 * starts reading from an address preceding linear_address!!!
 		 */
 		start_linear_address =
-			linear->surface.level[linear_level].offset +
+			linear->surface.u.legacy.level[linear_level].offset +
 			bpp * (linear_z * linear_slice_pitch +
 			       linear_y * linear_pitch +
 			       linear_x);
 		start_linear_address -= (int)(bpp * (tiled_x % granularity));
 
 		end_linear_address =
-			linear->surface.level[linear_level].offset +
+			linear->surface.u.legacy.level[linear_level].offset +
 			bpp * ((linear_z + copy_depth - 1) * linear_slice_pitch +
 			       (linear_y + copy_height - 1) * linear_pitch +
 			       (linear_x + copy_width));
@@ -379,7 +379,7 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
 		    copy_width_aligned % xalign == 0 &&
 		    tiled_micro_mode != V_009910_ADDR_SURF_ROTATED_MICRO_TILING &&
 		    /* check if everything fits into the bitfields */
-		    tiled->surface.tile_split <= 4096 &&
+		    tiled->surface.u.legacy.tile_split <= 4096 &&
 		    pitch_tile_max < (1 << 11) &&
 		    slice_tile_max < (1 << 22) &&
 		    linear_pitch <= (1 << 14) &&
@@ -423,8 +423,8 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
 	    /* check if these fit into the bitfields */
 	    src_address % 256 == 0 &&
 	    dst_address % 256 == 0 &&
-	    rsrc->surface.tile_split <= 4096 &&
-	    rdst->surface.tile_split <= 4096 &&
+	    rsrc->surface.u.legacy.tile_split <= 4096 &&
+	    rdst->surface.u.legacy.tile_split <= 4096 &&
 	    dstx % 8 == 0 &&
 	    dsty % 8 == 0 &&
 	    srcx % 8 == 0 &&