radeonsi: remove r600_common_context

Acked-by: Timothy Arceri <[email protected]>

7 files changed, 19 insertions, 122 deletions

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index 792f2827ee6..66e9a0b7819 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -297,109 +297,6 @@ struct radeon_saved_cs {
 	unsigned			bo_count;
 };
 
-struct r600_common_context {
-	struct pipe_context b; /* base class */
-
-	struct radeon_winsys		*ws;
-	struct radeon_winsys_ctx	*ctx;
-	enum radeon_family		family;
-	enum chip_class			chip_class;
-	struct radeon_winsys_cs		*gfx_cs;
-	struct radeon_winsys_cs		*dma_cs;
-	struct pipe_fence_handle	*last_gfx_fence;
-	struct pipe_fence_handle	*last_sdma_fence;
-	struct r600_resource		*eop_bug_scratch;
-	struct u_upload_mgr		*cached_gtt_allocator;
-	unsigned			num_gfx_cs_flushes;
-	unsigned			initial_gfx_cs_size;
-	unsigned			gpu_reset_counter;
-	unsigned			last_dirty_tex_counter;
-	unsigned			last_compressed_colortex_counter;
-	unsigned			last_num_draw_calls;
-
-	struct threaded_context		*tc;
-	struct u_suballocator		*allocator_zeroed_memory;
-	struct slab_child_pool		pool_transfers;
-	struct slab_child_pool		pool_transfers_unsync; /* for threaded_context */
-
-	/* Current unaccounted memory usage. */
-	uint64_t			vram;
-	uint64_t			gtt;
-
-	/* Additional context states. */
-	unsigned flags; /* flush flags */
-
-	/* Queries. */
-	/* Maintain the list of active queries for pausing between IBs. */
-	int				num_occlusion_queries;
-	int				num_perfect_occlusion_queries;
-	struct list_head		active_queries;
-	unsigned			num_cs_dw_queries_suspend;
-	/* Misc stats. */
-	unsigned			num_draw_calls;
-	unsigned			num_decompress_calls;
-	unsigned			num_mrt_draw_calls;
-	unsigned			num_prim_restart_calls;
-	unsigned			num_spill_draw_calls;
-	unsigned			num_compute_calls;
-	unsigned			num_spill_compute_calls;
-	unsigned			num_dma_calls;
-	unsigned			num_cp_dma_calls;
-	unsigned			num_vs_flushes;
-	unsigned			num_ps_flushes;
-	unsigned			num_cs_flushes;
-	unsigned			num_cb_cache_flushes;
-	unsigned			num_db_cache_flushes;
-	unsigned			num_L2_invalidates;
-	unsigned			num_L2_writebacks;
-	unsigned			num_resident_handles;
-	uint64_t			num_alloc_tex_transfer_bytes;
-	unsigned			last_tex_ps_draw_ratio; /* for query */
-
-	/* Render condition. */
-	struct r600_atom		render_cond_atom;
-	struct pipe_query		*render_cond;
-	unsigned			render_cond_mode;
-	bool				render_cond_invert;
-	bool				render_cond_force_off; /* for u_blitter */
-
-	/* Statistics gathering for the DCC enablement heuristic. It can't be
-	 * in r600_texture because r600_texture can be shared by multiple
-	 * contexts. This is for back buffers only. We shouldn't get too many
-	 * of those.
-	 *
-	 * X11 DRI3 rotates among a finite set of back buffers. They should
-	 * all fit in this array. If they don't, separate DCC might never be
-	 * enabled by DCC stat gathering.
-	 */
-	struct {
-		struct r600_texture		*tex;
-		/* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
-		struct pipe_query		*ps_stats[3];
-		/* If all slots are used and another slot is needed,
-		 * the least recently used slot is evicted based on this. */
-		int64_t				last_use_timestamp;
-		bool				query_active;
-	} dcc_stats[5];
-
-	struct pipe_device_reset_callback device_reset_callback;
-	struct u_log_context		*log;
-
-	void				*query_result_shader;
-
-	/* Copy one resource to another using async DMA. */
-	void (*dma_copy)(struct pipe_context *ctx,
-			 struct pipe_resource *dst,
-			 unsigned dst_level,
-			 unsigned dst_x, unsigned dst_y, unsigned dst_z,
-			 struct pipe_resource *src,
-			 unsigned src_level,
-			 const struct pipe_box *src_box);
-
-	void (*dma_clear_buffer)(struct si_context *sctx, struct pipe_resource *dst,
-				 uint64_t offset, uint64_t size, unsigned value);
-};
-
 /* r600_perfcounters.c */
 void si_perfcounters_destroy(struct si_screen *sscreen);
 
diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c
index 3a680a32449..92336ed377d 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -1364,7 +1364,7 @@ struct pipe_video_codec *si_common_uvd_create_decoder(struct pipe_context *conte
 						      ruvd_set_dtb set_dtb)
 {
 	struct si_context *sctx = (struct si_context*)context;
-	struct radeon_winsys *ws = sctx->b.ws;
+	struct radeon_winsys *ws = sctx->ws;
 	unsigned dpb_size;
 	unsigned width = templ->width, height = templ->height;
 	unsigned bs_buf_size;
@@ -1411,12 +1411,12 @@ struct pipe_video_codec *si_common_uvd_create_decoder(struct pipe_context *conte
 	dec->base.end_frame = ruvd_end_frame;
 	dec->base.flush = ruvd_flush;
 
-	dec->stream_type = profile2stream_type(dec, sctx->b.family);
+	dec->stream_type = profile2stream_type(dec, sctx->family);
 	dec->set_dtb = set_dtb;
 	dec->stream_handle = si_vid_alloc_stream_handle();
 	dec->screen = context->screen;
 	dec->ws = ws;
-	dec->cs = ws->cs_create(sctx->b.ctx, RING_UVD, NULL, NULL);
+	dec->cs = ws->cs_create(sctx->ctx, RING_UVD, NULL, NULL);
 	if (!dec->cs) {
 		RVID_ERR("Can't get command submission context.\n");
 		goto error;
@@ -1424,7 +1424,7 @@ struct pipe_video_codec *si_common_uvd_create_decoder(struct pipe_context *conte
 
 	for (i = 0; i < 16; i++)
 		 dec->render_pic_list[i] = NULL;
-	dec->fb_size = (sctx->b.family == CHIP_TONGA) ? FB_BUFFER_SIZE_TONGA :
+	dec->fb_size = (sctx->family == CHIP_TONGA) ? FB_BUFFER_SIZE_TONGA :
 			FB_BUFFER_SIZE;
 	bs_buf_size = width * height * (512 / (16 * 16));
 	for (i = 0; i < NUM_BUFFERS; ++i) {
@@ -1457,7 +1457,7 @@ struct pipe_video_codec *si_common_uvd_create_decoder(struct pipe_context *conte
 		si_vid_clear_buffer(context, &dec->dpb);
 	}
 
-	if (dec->stream_type == RUVD_CODEC_H264_PERF && sctx->b.family >= CHIP_POLARIS10) {
+	if (dec->stream_type == RUVD_CODEC_H264_PERF && sctx->family >= CHIP_POLARIS10) {
 		unsigned ctx_size = calc_ctx_size_h264_perf(dec);
 		if (!si_vid_create_buffer(dec->screen, &dec->ctx, ctx_size, PIPE_USAGE_DEFAULT)) {
 			RVID_ERR("Can't allocated context buffer.\n");
@@ -1466,7 +1466,7 @@ struct pipe_video_codec *si_common_uvd_create_decoder(struct pipe_context *conte
 		si_vid_clear_buffer(context, &dec->ctx);
 	}
 
-	if (sctx->b.family >= CHIP_POLARIS10 && sctx->screen->info.drm_minor >= 3) {
+	if (sctx->family >= CHIP_POLARIS10 && sctx->screen->info.drm_minor >= 3) {
 		if (!si_vid_create_buffer(dec->screen, &dec->sessionctx,
 					UVD_SESSION_CONTEXT_SIZE,
 					PIPE_USAGE_DEFAULT)) {
@@ -1476,7 +1476,7 @@ struct pipe_video_codec *si_common_uvd_create_decoder(struct pipe_context *conte
 		si_vid_clear_buffer(context, &dec->sessionctx);
 	}
 
-	if (sctx->b.family >= CHIP_VEGA10) {
+	if (sctx->family >= CHIP_VEGA10) {
 		dec->reg.data0 = RUVD_GPCOM_VCPU_DATA0_SOC15;
 		dec->reg.data1 = RUVD_GPCOM_VCPU_DATA1_SOC15;
 		dec->reg.cmd = RUVD_GPCOM_VCPU_CMD_SOC15;
diff --git a/src/gallium/drivers/radeon/radeon_uvd_enc.c b/src/gallium/drivers/radeon/radeon_uvd_enc.c
index 94bd26a08b5..521d08f304c 100644
--- a/src/gallium/drivers/radeon/radeon_uvd_enc.c
+++ b/src/gallium/drivers/radeon/radeon_uvd_enc.c
@@ -285,7 +285,7 @@ radeon_uvd_create_encoder(struct pipe_context *context,
                           radeon_uvd_enc_get_buffer get_buffer)
 {
    struct si_screen *sscreen = (struct si_screen *) context->screen;
-   struct r600_common_context *rctx = (struct r600_common_context *) context;
+   struct si_context *sctx = (struct si_context *) context;
    struct radeon_uvd_encoder *enc;
    struct pipe_video_buffer *tmp_buf, templat = { };
    struct radeon_surf *tmp_surf;
@@ -314,7 +314,7 @@ radeon_uvd_create_encoder(struct pipe_context *context,
    enc->screen = context->screen;
    enc->ws = ws;
    enc->cs =
-      ws->cs_create(rctx->ctx, RING_UVD_ENC, radeon_uvd_enc_cs_flush, enc);
+      ws->cs_create(sctx->ctx, RING_UVD_ENC, radeon_uvd_enc_cs_flush, enc);
 
    if (!enc->cs) {
       RVID_ERR("Can't get command submission context.\n");
diff --git a/src/gallium/drivers/radeon/radeon_vce.c b/src/gallium/drivers/radeon/radeon_vce.c
index 9eac217c1c0..57b9d349582 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -437,7 +437,7 @@ struct pipe_video_codec *si_vce_create_encoder(struct pipe_context *context,
 
 	enc->screen = context->screen;
 	enc->ws = ws;
-	enc->cs = ws->cs_create(sctx->b.ctx, RING_VCE, rvce_cs_flush, enc);
+	enc->cs = ws->cs_create(sctx->ctx, RING_VCE, rvce_cs_flush, enc);
 	if (!enc->cs) {
 		RVID_ERR("Can't get command submission context.\n");
 		goto error;
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index db4e24f9d76..48d79ffb9f9 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -1199,7 +1199,7 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
 					     const struct pipe_video_codec *templ)
 {
 	struct si_context *sctx = (struct si_context*)context;
-	struct radeon_winsys *ws = sctx->b.ws;
+	struct radeon_winsys *ws = sctx->ws;
 	unsigned width = templ->width, height = templ->height;
 	unsigned dpb_size, bs_buf_size, stream_type = 0;
 	struct radeon_decoder *dec;
@@ -1253,7 +1253,7 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
 	dec->stream_handle = si_vid_alloc_stream_handle();
 	dec->screen = context->screen;
 	dec->ws = ws;
-	dec->cs = ws->cs_create(sctx->b.ctx, RING_VCN_DEC, NULL, NULL);
+	dec->cs = ws->cs_create(sctx->ctx, RING_VCN_DEC, NULL, NULL);
 	if (!dec->cs) {
 		RVID_ERR("Can't get command submission context.\n");
 		goto error;
diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.c b/src/gallium/drivers/radeon/radeon_vcn_enc.c
index 388a33388b3..8f9af73c664 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc.c
@@ -262,7 +262,7 @@ struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
 		radeon_enc_get_buffer get_buffer)
 {
 	struct si_screen *sscreen = (struct si_screen *)context->screen;
-	struct r600_common_context *rctx = (struct r600_common_context*)context;
+	struct si_context *sctx = (struct si_context*)context;
 	struct radeon_encoder *enc;
 	struct pipe_video_buffer *tmp_buf, templat = {};
 	struct radeon_surf *tmp_surf;
@@ -286,7 +286,7 @@ struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
 	enc->bits_in_shifter = 0;
 	enc->screen = context->screen;
 	enc->ws = ws;
-	enc->cs = ws->cs_create(rctx->ctx, RING_VCN_ENC, radeon_enc_cs_flush, enc);
+	enc->cs = ws->cs_create(sctx->ctx, RING_VCN_ENC, radeon_enc_cs_flush, enc);
 
 	if (!enc->cs) {
 		RVID_ERR("Can't get command submission context.\n");
diff --git a/src/gallium/drivers/radeon/radeon_video.c b/src/gallium/drivers/radeon/radeon_video.c
index b2238fb113e..a2947df9590 100644
--- a/src/gallium/drivers/radeon/radeon_video.c
+++ b/src/gallium/drivers/radeon/radeon_video.c
@@ -121,8 +121,8 @@ void si_vid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffe
 {
 	struct si_context *sctx = (struct si_context*)context;
 
-	sctx->b.dma_clear_buffer(sctx, &buffer->res->b.b, 0,
-				 buffer->res->buf->size, 0);
+	sctx->dma_clear_buffer(sctx, &buffer->res->b.b, 0,
+			       buffer->res->buf->size, 0);
 	context->flush(context, NULL, 0);
 }
 
@@ -134,7 +134,7 @@ void si_vid_join_surfaces(struct si_context *sctx,
 			  struct pb_buffer** buffers[VL_NUM_COMPONENTS],
 			  struct radeon_surf *surfaces[VL_NUM_COMPONENTS])
 {
-	struct radeon_winsys *ws = sctx->b.ws;;
+	struct radeon_winsys *ws = sctx->ws;;
 	unsigned best_tiling, best_wh, off;
 	unsigned size, alignment;
 	struct pb_buffer *pb;
@@ -146,7 +146,7 @@ void si_vid_join_surfaces(struct si_context *sctx,
 		if (!surfaces[i])
 			continue;
 
-		if (sctx->b.chip_class < GFX9) {
+		if (sctx->chip_class < GFX9) {
 			/* choose the smallest bank w/h for now */
 			wh = surfaces[i]->u.legacy.bankw * surfaces[i]->u.legacy.bankh;
 			if (wh < best_wh) {
@@ -163,7 +163,7 @@ void si_vid_join_surfaces(struct si_context *sctx,
 		/* adjust the texture layer offsets */
 		off = align(off, surfaces[i]->surf_alignment);
 
-		if (sctx->b.chip_class < GFX9) {
+		if (sctx->chip_class < GFX9) {
 			/* copy the tiling parameters */
 			surfaces[i]->u.legacy.bankw = surfaces[best_tiling]->u.legacy.bankw;
 			surfaces[i]->u.legacy.bankh = surfaces[best_tiling]->u.legacy.bankh;