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authorMarek Olšák <[email protected]>2015-04-16 20:35:27 +0200
committerMarek Olšák <[email protected]>2015-08-14 15:02:29 +0200
commit8ba70e0a7405005c079eb72f94999245c992aa91 (patch)
tree6d8d02a418f7c3b2229e97eb1503c82b4be04f12 /src/gallium/drivers/radeon
parente7fc664b91a5d886c2709d05a498f6a1dfbaf136 (diff)
radeonsi: fix DRM version checks for amdgpu DRM 3.0.0
Diffstat (limited to 'src/gallium/drivers/radeon')
-rw-r--r--src/gallium/drivers/radeon/r600_buffer_common.c6
-rw-r--r--src/gallium/drivers/radeon/r600_pipe_common.c4
-rw-r--r--src/gallium/drivers/radeon/r600_texture.c8
3 files changed, 12 insertions, 6 deletions
diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
index 0f788b7e23c..cb9809f2449 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -121,7 +121,8 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
/* Older kernels didn't always flush the HDP cache before
* CS execution
*/
- if (rscreen->info.drm_minor < 40) {
+ if (rscreen->info.drm_major == 2 &&
+ rscreen->info.drm_minor < 40) {
res->domains = RADEON_DOMAIN_GTT;
flags |= RADEON_FLAG_GTT_WC;
break;
@@ -147,7 +148,8 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
* Write-combined CPU mappings are fine, the kernel ensures all CPU
* writes finish before the GPU executes a command stream.
*/
- if (rscreen->info.drm_minor < 40)
+ if (rscreen->info.drm_major == 2 &&
+ rscreen->info.drm_minor < 40)
res->domains = RADEON_DOMAIN_GTT;
else if (res->domains & RADEON_DOMAIN_VRAM)
flags |= RADEON_FLAG_CPU_ACCESS;
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
index 9e68e5f80ac..51c72cc882f 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -928,7 +928,9 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen,
pipe_mutex_init(rscreen->aux_context_lock);
pipe_mutex_init(rscreen->gpu_load_mutex);
- if (rscreen->info.drm_minor >= 28 && (rscreen->debug_flags & DBG_TRACE_CS)) {
+ if (((rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 28) ||
+ rscreen->info.drm_major == 3) &&
+ (rscreen->debug_flags & DBG_TRACE_CS)) {
rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->b,
PIPE_BIND_CUSTOM,
PIPE_USAGE_STAGING,
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index a4c7034cb37..54696910e43 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -490,7 +490,7 @@ static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
unsigned num_pipes = rscreen->tiling_info.num_channels;
if (rscreen->chip_class <= EVERGREEN &&
- rscreen->info.drm_minor < 26)
+ rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26)
return 0;
/* HW bug on R6xx. */
@@ -502,7 +502,7 @@ static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
/* HTILE is broken with 1D tiling on old kernels and CIK. */
if (rscreen->chip_class >= CIK &&
rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
- rscreen->info.drm_minor < 38)
+ rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
return 0;
switch (num_pipes) {
@@ -1261,7 +1261,9 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
/* fast color clear with 1D tiling doesn't work on old kernels and CIK */
if (tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
- rctx->chip_class >= CIK && rctx->screen->info.drm_minor < 38) {
+ rctx->chip_class >= CIK &&
+ rctx->screen->info.drm_major == 2 &&
+ rctx->screen->info.drm_minor < 38) {
continue;
}