radeonsi: pin the winsys thread to the requested L3 cache (v2)

v2: rebase

Reviewed-by: Brian Paul <[email protected]>

1 files changed, 8 insertions, 0 deletions

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 99a793f9028..bb732ab314b 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -257,6 +257,14 @@ struct radeon_winsys {
     void (*query_info)(struct radeon_winsys *ws,
                        struct radeon_info *info);
 
+    /**
+     * A hint for the winsys that it should pin its execution threads to
+     * a group of cores sharing a specific L3 cache if the CPU has multiple
+     * L3 caches. This is needed for good multithreading performance on
+     * AMD Zen CPUs.
+     */
+    void (*pin_threads_to_L3_cache)(struct radeon_winsys *ws, unsigned cache);
+
     /**************************************************************************
      * Buffer management. Buffer attributes are mostly fixed over its lifetime.
      *