diff options
| author | Tom Stellard <[email protected]> | 2012-06-28 20:27:55 +0000 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-06-29 18:46:18 +0000 |
| commit | a31b2f71076b9d3fe9bc5f2bae3228f1e7b99ee2 (patch) | |
| tree | a1eda2beecba9682d5c9a8815ce504f13dd9c046 /src/gallium/drivers/radeon | |
| parent | e17c586d08aee5bbaad6ac5efd2d30fe1d179406 (diff) | |
radeon/llvm: Enable vec4 loads on R600
Diffstat (limited to 'src/gallium/drivers/radeon')
| -rw-r--r-- | src/gallium/drivers/radeon/AMDGPUISelLowering.cpp | 3 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/R600CodeEmitter.cpp | 1 | ||||
| -rw-r--r-- | src/gallium/drivers/radeon/R600Instructions.td | 16 |
3 files changed, 20 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp index f14900450ae..ef5715fd5f0 100644 --- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp +++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp @@ -34,6 +34,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : setOperationAction(ISD::FRINT, MVT::f32, Legal); setOperationAction(ISD::LOAD, MVT::f32, Custom); + setOperationAction(ISD::LOAD, MVT::v4f32, Custom); setOperationAction(ISD::UDIV, MVT::i32, Expand); setOperationAction(ISD::UDIVREM, MVT::i32, Custom); @@ -139,6 +140,8 @@ SDValue AMDGPUTargetLowering::BitcastLOAD(SDValue Op, SelectionDAG &DAG) const if (VT == MVT::f32) { IntVT = MVT::i32; + } else if (VT == MVT::v4f32) { + IntVT = MVT::v4i32; } else { return Op; } diff --git a/src/gallium/drivers/radeon/R600CodeEmitter.cpp b/src/gallium/drivers/radeon/R600CodeEmitter.cpp index 99964d4beb1..9db6ba86232 100644 --- a/src/gallium/drivers/radeon/R600CodeEmitter.cpp +++ b/src/gallium/drivers/radeon/R600CodeEmitter.cpp @@ -205,6 +205,7 @@ bool R600CodeEmitter::runOnMachineFunction(MachineFunction &MF) { } case AMDIL::VTX_READ_PARAM_eg: case AMDIL::VTX_READ_GLOBAL_eg: + case AMDIL::VTX_READ_GLOBAL_128_eg: { uint64_t InstWord01 = getBinaryCodeForInstr(MI); uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td index fa52f32001d..da5f364839f 100644 --- a/src/gallium/drivers/radeon/R600Instructions.td +++ b/src/gallium/drivers/radeon/R600Instructions.td @@ -1029,6 +1029,21 @@ def VTX_READ_GLOBAL_eg : VTX_READ_32_eg <1, [(set (i32 R600_TReg32_X:$dst), (global_load ADDRVTX_READ:$ptr))] >; +class VTX_READ_128_eg <bits<8> buffer_id, list<dag> pattern> + : VTX_READ_eg <buffer_id, (outs R600_Reg128:$dst), pattern> { + + let MEGA_FETCH_COUNT = 16; + let DST_SEL_X = 0; + let DST_SEL_Y = 1; + let DST_SEL_Z = 2; + let DST_SEL_W = 3; + let DATA_FORMAT = 0x22; // COLOR_32_32_32_32 +} + +def VTX_READ_GLOBAL_128_eg : VTX_READ_128_eg <1, + [(set (v4i32 R600_Reg128:$dst), (global_load ADDRVTX_READ:$ptr))] +>; + } let Predicates = [isCayman] in { @@ -1280,5 +1295,6 @@ def : Vector_Build <v4i32, R600_Reg32>; def : BitConvert <i32, f32, R600_Reg32>; def : BitConvert <f32, i32, R600_Reg32>; +def : BitConvert <v4f32, v4i32, R600_Reg128>; } // End isR600toCayman Predicate |