r600g,radeonsi: consolidate tiling_info initialization

and the util_format_s3tc_init calls too.

2 files changed, 129 insertions, 2 deletions

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
index 24e0e7a0024..06484553b02 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -26,6 +26,7 @@
 
 #include "r600_pipe_common.h"
 #include "tgsi/tgsi_parse.h"
+#include "util/u_format_s3tc.h"
 
 static const struct debug_named_value common_debug_options[] = {
 	/* logging */
@@ -44,7 +45,119 @@ static const struct debug_named_value common_debug_options[] = {
 	DEBUG_NAMED_VALUE_END /* must be last */
 };
 
-void r600_common_screen_init(struct r600_common_screen *rscreen,
+static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
+				  uint32_t tiling_config)
+{
+	switch ((tiling_config & 0xe) >> 1) {
+	case 0:
+		rscreen->tiling_info.num_channels = 1;
+		break;
+	case 1:
+		rscreen->tiling_info.num_channels = 2;
+		break;
+	case 2:
+		rscreen->tiling_info.num_channels = 4;
+		break;
+	case 3:
+		rscreen->tiling_info.num_channels = 8;
+		break;
+	default:
+		return false;
+	}
+
+	switch ((tiling_config & 0x30) >> 4) {
+	case 0:
+		rscreen->tiling_info.num_banks = 4;
+		break;
+	case 1:
+		rscreen->tiling_info.num_banks = 8;
+		break;
+	default:
+		return false;
+
+	}
+	switch ((tiling_config & 0xc0) >> 6) {
+	case 0:
+		rscreen->tiling_info.group_bytes = 256;
+		break;
+	case 1:
+		rscreen->tiling_info.group_bytes = 512;
+		break;
+	default:
+		return false;
+	}
+	return true;
+}
+
+static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
+				       uint32_t tiling_config)
+{
+	switch (tiling_config & 0xf) {
+	case 0:
+		rscreen->tiling_info.num_channels = 1;
+		break;
+	case 1:
+		rscreen->tiling_info.num_channels = 2;
+		break;
+	case 2:
+		rscreen->tiling_info.num_channels = 4;
+		break;
+	case 3:
+		rscreen->tiling_info.num_channels = 8;
+		break;
+	default:
+		return false;
+	}
+
+	switch ((tiling_config & 0xf0) >> 4) {
+	case 0:
+		rscreen->tiling_info.num_banks = 4;
+		break;
+	case 1:
+		rscreen->tiling_info.num_banks = 8;
+		break;
+	case 2:
+		rscreen->tiling_info.num_banks = 16;
+		break;
+	default:
+		return false;
+	}
+
+	switch ((tiling_config & 0xf00) >> 8) {
+	case 0:
+		rscreen->tiling_info.group_bytes = 256;
+		break;
+	case 1:
+		rscreen->tiling_info.group_bytes = 512;
+		break;
+	default:
+		return false;
+	}
+	return true;
+}
+
+static bool r600_init_tiling(struct r600_common_screen *rscreen)
+{
+	uint32_t tiling_config = rscreen->info.r600_tiling_config;
+
+	/* set default group bytes, overridden by tiling info ioctl */
+	if (rscreen->chip_class <= R700) {
+		rscreen->tiling_info.group_bytes = 256;
+	} else {
+		rscreen->tiling_info.group_bytes = 512;
+	}
+
+	if (!tiling_config)
+		return true;
+
+	if (rscreen->chip_class <= R700) {
+		return r600_interpret_tiling(rscreen, tiling_config);
+	} else {
+		return evergreen_interpret_tiling(rscreen, tiling_config);
+	}
+}
+
+bool r600_common_screen_init(struct r600_common_screen *rscreen,
 			     struct radeon_winsys *ws)
 {
 	ws->query_info(ws, &rscreen->info);
@@ -54,9 +167,16 @@ void r600_common_screen_init(struct r600_common_screen *rscreen,
 	rscreen->chip_class = rscreen->info.chip_class;
 	rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
 
+	if (!r600_init_tiling(rscreen)) {
+		return false;
+	}
+
+	util_format_s3tc_init();
+
 	/* Create the auxiliary context. */
 	pipe_mutex_init(rscreen->aux_context_lock);
 	rscreen->aux_context = rscreen->b.context_create(&rscreen->b, NULL);
+	return true;
 }
 
 void r600_common_screen_cleanup(struct r600_common_screen *rscreen)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index 86730be15c3..e5e79b08d61 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -144,12 +144,19 @@ struct r600_texture {
 	unsigned			mipmap_shift;
 };
 
+struct r600_tiling_info {
+	unsigned num_channels;
+	unsigned num_banks;
+	unsigned group_bytes;
+};
+
 struct r600_common_screen {
 	struct pipe_screen		b;
 	struct radeon_winsys		*ws;
 	enum radeon_family		family;
 	enum chip_class			chip_class;
 	struct radeon_info		info;
+	struct r600_tiling_info		tiling_info;
 	unsigned			debug_flags;
 
 	/* Auxiliary context. Mainly used to initialize resources.
@@ -239,7 +246,7 @@ struct r600_common_context {
 };
 
 /* r600_common_pipe.c */
-void r600_common_screen_init(struct r600_common_screen *rscreen,
+bool r600_common_screen_init(struct r600_common_screen *rscreen,
 			     struct radeon_winsys *ws);
 void r600_common_screen_cleanup(struct r600_common_screen *rscreen);
 bool r600_common_context_init(struct r600_common_context *rctx,