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authorMarek Olšák <[email protected]>2015-02-10 14:16:56 +0100
committerMarek Olšák <[email protected]>2015-02-17 17:31:48 +0100
commit218b15715ec6a9e987ae78d904683801e5ccdf4b (patch)
treeb0d0440218e263cbfa63bb0901773f45af60a0e8 /src/gallium/drivers/radeon
parenta27b74819ad375e8c0bc88e13f42c951d2b5cd6a (diff)
radeonsi: initialize TC_L2_dirty to false after buffer allocation
I forgot to do this, though "true" should have no effect on correctness. Reviewed-by: Michel Dänzer <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeon')
-rw-r--r--src/gallium/drivers/radeon/r600_buffer_common.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c
index b7306d7bf34..ebe80671536 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -185,6 +185,7 @@ bool r600_init_resource(struct r600_common_screen *rscreen,
pb_reference(&old_buf, NULL);
util_range_set_empty(&res->valid_buffer_range);
+ res->TC_L2_dirty = false;
if (rscreen->debug_flags & DBG_VM && res->b.b.target == PIPE_BUFFER) {
fprintf(stderr, "VM start=0x%"PRIX64" end=0x%"PRIX64" | Buffer %u bytes\n",