diff options
| author | Marek Olšák <[email protected]> | 2014-07-26 17:15:39 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2014-07-28 23:57:08 +0200 |
| commit | a9528cef6b6ff4875c9d125a60b7309a2ad24766 (patch) | |
| tree | d77513f18015b67ea4dcf3b6b8c119385aa9955f /src/gallium/drivers/radeon | |
| parent | 71ce92200e0314a0878088dec8c0c2a0270bc4dc (diff) | |
r600g,radeonsi: switch all occurences of array_size to util_max_layer
This fixes 3D texture support in all these cases, because array_size is 1
with 3D textures and depth0 actually contains the "array size".
util_max_layer is universal and returns the last layer index for any texture
target.
A lot of the cases below can't actually be hit with 3D textures, but let's
be consistent.
This fixes a failure in:
piglit layered-rendering/clear-color-all-types 3d single_level
for r600g and radeonsi, which was caused by an incorrect CMASK size
calculation.
Cc: [email protected]
Reviewed-by: Michel Dänzer <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeon')
| -rw-r--r-- | src/gallium/drivers/radeon/r600_texture.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index ac9f6808b3e..482bbff4e63 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -380,7 +380,8 @@ void r600_texture_get_cmask_info(struct r600_common_screen *rscreen, out->slice_tile_max = ((pitch_elements * height) / (128*128)) - 1; out->alignment = MAX2(256, base_align); - out->size = rtex->surface.array_size * align(slice_bytes, base_align); + out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) * + align(slice_bytes, base_align); } static void si_texture_get_cmask_info(struct r600_common_screen *rscreen, @@ -427,7 +428,8 @@ static void si_texture_get_cmask_info(struct r600_common_screen *rscreen, out->slice_tile_max -= 1; out->alignment = MAX2(256, base_align); - out->size = rtex->surface.array_size * align(slice_bytes, base_align); + out->size = (util_max_layer(&rtex->resource.b.b, 0) + 1) * + align(slice_bytes, base_align); } static void r600_texture_allocate_cmask(struct r600_common_screen *rscreen, @@ -523,7 +525,8 @@ static unsigned si_texture_htile_alloc_size(struct r600_common_screen *rscreen, pipe_interleave_bytes = rscreen->tiling_info.group_bytes; base_align = num_pipes * pipe_interleave_bytes; - return rtex->surface.array_size * align(slice_bytes, base_align); + return (util_max_layer(&rtex->resource.b.b, 0) + 1) * + align(slice_bytes, base_align); } static unsigned r600_texture_htile_alloc_size(struct r600_common_screen *rscreen, |