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authorBas Nieuwenhuizen <[email protected]>2016-03-25 02:06:50 +0100
committerBas Nieuwenhuizen <[email protected]>2016-04-02 01:51:13 +0200
commit1a5c8c24b5791efa02a7beefa4ba1c49ae033c73 (patch)
treec63783871510b1ba41d5a12f187f51a336a6b79a /src/gallium/drivers/radeon
parentbe5899dcf9a337548d8095a00060d4451b0df222 (diff)
gallium: distinguish between shader IR in get_compute_param
For radeonsi, native and TGSI use different compilers and this results in different limits for different IR's. The set we strictly need for radeonsi is only the MAX_BLOCK_SIZE and MAX_THREADS_PER_BLOCK params, but I added a few others as shader related that seemed like they would also typically depend on the compiler. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeon')
-rw-r--r--src/gallium/drivers/radeon/r600_pipe_common.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
index 720fc06ece2..32bd6e40d32 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -612,6 +612,7 @@ const char *r600_get_llvm_processor_name(enum radeon_family family)
}
static int r600_get_compute_param(struct pipe_screen *screen,
+ enum pipe_shader_ir ir_type,
enum pipe_compute_cap param,
void *ret)
{
@@ -678,7 +679,7 @@ static int r600_get_compute_param(struct pipe_screen *screen,
uint64_t *max_global_size = ret;
uint64_t max_mem_alloc_size;
- r600_get_compute_param(screen,
+ r600_get_compute_param(screen, ir_type,
PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
&max_mem_alloc_size);