gallium/radeon: tell the winsys the exact resource binding types

Use the priority flags and expand them.
This information will be used for debugging.

Reviewed-by: Michel Dänzer <[email protected]>

6 files changed, 75 insertions, 23 deletions

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index 2df93e54559..0f9b91af315 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -623,6 +623,18 @@ static inline unsigned r600_wavefront_size(enum radeon_family family)
 	}
 }
 
+static inline enum radeon_bo_priority
+r600_get_sampler_view_priority(struct r600_resource *res)
+{
+	if (res->b.b.target == PIPE_BUFFER)
+		return RADEON_PRIO_SAMPLER_BUFFER;
+
+	if (res->b.b.nr_samples > 1)
+		return RADEON_PRIO_SAMPLER_TEXTURE_MSAA;
+
+	return RADEON_PRIO_SAMPLER_TEXTURE;
+}
+
 #define COMPUTE_DBG(rscreen, fmt, args...) \
 	do { \
 		if ((rscreen->b.debug_flags & DBG_COMPUTE)) fprintf(stderr, fmt, ##args); \
diff --git a/src/gallium/drivers/radeon/r600_query.c b/src/gallium/drivers/radeon/r600_query.c
index deeae0a6a65..9a5402583f4 100644
--- a/src/gallium/drivers/radeon/r600_query.c
+++ b/src/gallium/drivers/radeon/r600_query.c
@@ -226,7 +226,7 @@ static void r600_emit_query_begin(struct r600_common_context *ctx, struct r600_q
 		assert(0);
 	}
 	r600_emit_reloc(ctx, &ctx->rings.gfx, query->buffer.buf, RADEON_USAGE_WRITE,
-			RADEON_PRIO_MIN);
+			RADEON_PRIO_QUERY);
 
 	if (r600_is_timer_query(query->type))
 		ctx->num_cs_dw_timer_queries_suspend += query->num_cs_dw;
@@ -288,7 +288,7 @@ static void r600_emit_query_end(struct r600_common_context *ctx, struct r600_que
 		assert(0);
 	}
 	r600_emit_reloc(ctx, &ctx->rings.gfx, query->buffer.buf, RADEON_USAGE_WRITE,
-			RADEON_PRIO_MIN);
+			RADEON_PRIO_QUERY);
 
 	query->buffer.results_end += query->result_size;
 
@@ -344,7 +344,7 @@ static void r600_emit_query_predication(struct r600_common_context *ctx, struct
 				radeon_emit(cs, va + results_base);
 				radeon_emit(cs, op | (((va + results_base) >> 32) & 0xFF));
 				r600_emit_reloc(ctx, &ctx->rings.gfx, qbuf->buf, RADEON_USAGE_READ,
-						RADEON_PRIO_MIN);
+						RADEON_PRIO_QUERY);
 				results_base += query->result_size;
 	
 				/* set CONTINUE bit for all packets except the first */
@@ -990,7 +990,8 @@ void r600_query_init_backend_mask(struct r600_common_context *ctx)
 		radeon_emit(cs, buffer->gpu_address);
 		radeon_emit(cs, buffer->gpu_address >> 32);
 
-		r600_emit_reloc(ctx, &ctx->rings.gfx, buffer, RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
+		r600_emit_reloc(ctx, &ctx->rings.gfx, buffer,
+                                RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
 
 		/* analyze results */
 		results = r600_buffer_map_sync_with_rings(ctx, buffer, PIPE_TRANSFER_READ);
diff --git a/src/gallium/drivers/radeon/r600_streamout.c b/src/gallium/drivers/radeon/r600_streamout.c
index 5198f1e041d..33403b572af 100644
--- a/src/gallium/drivers/radeon/r600_streamout.c
+++ b/src/gallium/drivers/radeon/r600_streamout.c
@@ -217,7 +217,7 @@ static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r
 			radeon_emit(cs, va >> 8);			/* BUFFER_BASE */
 
 			r600_emit_reloc(rctx, &rctx->rings.gfx, r600_resource(t[i]->b.buffer),
-					RADEON_USAGE_WRITE, RADEON_PRIO_SHADER_RESOURCE_RW);
+					RADEON_USAGE_WRITE, RADEON_PRIO_RINGS_STREAMOUT);
 
 			/* R7xx requires this packet after updating BUFFER_BASE.
 			 * Without this, R7xx locks up. */
@@ -227,7 +227,7 @@ static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r
 				radeon_emit(cs, va >> 8);
 
 				r600_emit_reloc(rctx, &rctx->rings.gfx, r600_resource(t[i]->b.buffer),
-						RADEON_USAGE_WRITE, RADEON_PRIO_SHADER_RESOURCE_RW);
+						RADEON_USAGE_WRITE, RADEON_PRIO_RINGS_STREAMOUT);
 			}
 		}
 
@@ -245,7 +245,7 @@ static void r600_emit_streamout_begin(struct r600_common_context *rctx, struct r
 			radeon_emit(cs, va >> 32); /* src address hi */
 
 			r600_emit_reloc(rctx,  &rctx->rings.gfx, t[i]->buf_filled_size,
-					RADEON_USAGE_READ, RADEON_PRIO_MIN);
+					RADEON_USAGE_READ, RADEON_PRIO_SO_FILLED_SIZE);
 		} else {
 			/* Start from the beginning. */
 			radeon_emit(cs, PKT3(PKT3_STRMOUT_BUFFER_UPDATE, 4, 0));
@@ -289,7 +289,7 @@ void r600_emit_streamout_end(struct r600_common_context *rctx)
 		radeon_emit(cs, 0); /* unused */
 
 		r600_emit_reloc(rctx,  &rctx->rings.gfx, t[i]->buf_filled_size,
-				RADEON_USAGE_WRITE, RADEON_PRIO_MIN);
+				RADEON_USAGE_WRITE, RADEON_PRIO_SO_FILLED_SIZE);
 
 		/* Zero the buffer size. The counters (primitives generated,
 		 * primitives emitted) may be enabled even if there is not
diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c
index 81f3f45db9f..4c59885eecf 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -111,7 +111,7 @@ static void send_cmd(struct ruvd_decoder *dec, unsigned cmd,
 	int reloc_idx;
 
 	reloc_idx = dec->ws->cs_add_reloc(dec->cs, cs_buf, usage, domain,
-					  RADEON_PRIO_MIN);
+					  RADEON_PRIO_UVD);
 	if (!dec->use_legacy) {
 		uint64_t addr;
 		addr = dec->ws->buffer_get_virtual_address(cs_buf);
diff --git a/src/gallium/drivers/radeon/radeon_vce.c b/src/gallium/drivers/radeon/radeon_vce.c
index 7eab974a3df..0e01e91d02b 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -516,7 +516,7 @@ void rvce_add_buffer(struct rvce_encoder *enc, struct radeon_winsys_cs_handle *b
 {
 	int reloc_idx;
 
-	reloc_idx = enc->ws->cs_add_reloc(enc->cs, buf, usage, domain, RADEON_PRIO_MIN);
+	reloc_idx = enc->ws->cs_add_reloc(enc->cs, buf, usage, domain, RADEON_PRIO_VCE);
 	if (enc->use_vm) {
 		uint64_t addr;
 		addr = enc->ws->buffer_get_virtual_address(buf);
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 00accd5b3e6..8b17281efe7 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -178,20 +178,59 @@ enum radeon_value_id {
     RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
 };
 
+/* Each group of four has the same priority. */
 enum radeon_bo_priority {
-    RADEON_PRIO_MIN,
-    RADEON_PRIO_SHADER_DATA, /* shader code, resource descriptors */
-    RADEON_PRIO_SHADER_BUFFER_RO, /* read-only */
-    RADEON_PRIO_SHADER_TEXTURE_RO, /* read-only */
-    RADEON_PRIO_SHADER_RESOURCE_RW, /* buffers, textures, streamout, GS rings, RATs; read/write */
-    RADEON_PRIO_COLOR_BUFFER,
-    RADEON_PRIO_DEPTH_BUFFER,
-    RADEON_PRIO_SHADER_TEXTURE_MSAA,
-    RADEON_PRIO_COLOR_BUFFER_MSAA,
-    RADEON_PRIO_DEPTH_BUFFER_MSAA,
-    RADEON_PRIO_COLOR_META,
-    RADEON_PRIO_DEPTH_META,
-    RADEON_PRIO_MAX /* must be <= 15 */
+    RADEON_PRIO_FENCE = 0,
+    RADEON_PRIO_TRACE,
+    RADEON_PRIO_SO_FILLED_SIZE,
+    RADEON_PRIO_QUERY,
+
+    RADEON_PRIO_IB1 = 4, /* main IB submitted to the kernel */
+    RADEON_PRIO_IB2, /* IB executed with INDIRECT_BUFFER */
+    RADEON_PRIO_DRAW_INDIRECT,
+    RADEON_PRIO_INDEX_BUFFER,
+
+    RADEON_PRIO_CP_DMA = 8,
+
+    RADEON_PRIO_VCE = 12,
+    RADEON_PRIO_UVD,
+    RADEON_PRIO_SDMA_BUFFER,
+    RADEON_PRIO_SDMA_TEXTURE,
+
+    RADEON_PRIO_USER_SHADER = 16,
+    RADEON_PRIO_INTERNAL_SHADER, /* fetch shader, etc. */
+
+    /* gap: 20 */
+
+    RADEON_PRIO_CONST_BUFFER = 24,
+    RADEON_PRIO_DESCRIPTORS,
+    RADEON_PRIO_BORDER_COLORS,
+
+    RADEON_PRIO_SAMPLER_BUFFER = 28,
+    RADEON_PRIO_VERTEX_BUFFER,
+
+    RADEON_PRIO_SHADER_RW_BUFFER = 32,
+    RADEON_PRIO_RINGS_STREAMOUT,
+    RADEON_PRIO_SCRATCH_BUFFER,
+    RADEON_PRIO_COMPUTE_GLOBAL,
+
+    RADEON_PRIO_SAMPLER_TEXTURE = 36,
+    RADEON_PRIO_SHADER_RW_IMAGE,
+
+    RADEON_PRIO_SAMPLER_TEXTURE_MSAA = 40,
+
+    RADEON_PRIO_COLOR_BUFFER = 44,
+
+    RADEON_PRIO_DEPTH_BUFFER = 48,
+
+    RADEON_PRIO_COLOR_BUFFER_MSAA = 52,
+
+    RADEON_PRIO_DEPTH_BUFFER_MSAA = 56,
+
+    RADEON_PRIO_CMASK = 60,
+    RADEON_PRIO_DCC,
+    RADEON_PRIO_HTILE,
+    /* 63 is the maximum value */
 };
 
 struct winsys_handle;