r600g: move some debug options to drivers/radeon

2 files changed, 33 insertions, 0 deletions

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
index cdfdc19bd0e..9d68f4ba7ab 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -26,6 +26,23 @@
 
 #include "r600_pipe_common.h"
 
+static const struct debug_named_value common_debug_options[] = {
+	/* logging */
+	{ "texdepth", DBG_TEX_DEPTH, "Print texture depth info" },
+	{ "compute", DBG_COMPUTE, "Print compute info" },
+	{ "vm", DBG_VM, "Print virtual addresses when creating resources" },
+	{ "trace_cs", DBG_TRACE_CS, "Trace cs and write rlockup_<csid>.c file with faulty cs" },
+
+	/* shaders */
+	{ "fs", DBG_FS, "Print fetch shaders" },
+	{ "vs", DBG_VS, "Print vertex shaders" },
+	{ "gs", DBG_GS, "Print geometry shaders" },
+	{ "ps", DBG_PS, "Print pixel shaders" },
+	{ "cs", DBG_CS, "Print compute shaders" },
+
+	DEBUG_NAMED_VALUE_END /* must be last */
+};
+
 void r600_common_screen_init(struct r600_common_screen *rscreen,
 			     struct radeon_winsys *ws)
 {
@@ -34,6 +51,7 @@ void r600_common_screen_init(struct r600_common_screen *rscreen,
 	rscreen->ws = ws;
 	rscreen->family = rscreen->info.family;
 	rscreen->chip_class = rscreen->info.chip_class;
+	rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
 }
 
 bool r600_common_context_init(struct r600_common_context *rctx,
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index d83876df824..63bc9b1fade 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -59,6 +59,20 @@
 #define R600_CONTEXT_WAIT_3D_IDLE		(1 << 17)
 #define R600_CONTEXT_WAIT_CP_DMA_IDLE		(1 << 18)
 
+/* Debug flags. */
+/* logging */
+#define DBG_TEX_DEPTH		(1 << 0)
+#define DBG_COMPUTE		(1 << 1)
+#define DBG_VM			(1 << 2)
+#define DBG_TRACE_CS		(1 << 3)
+/* shaders */
+#define DBG_FS			(1 << 8)
+#define DBG_VS			(1 << 9)
+#define DBG_GS			(1 << 10)
+#define DBG_PS			(1 << 11)
+#define DBG_CS			(1 << 12)
+/* The maximum allowed bit is 15. */
+
 struct r600_common_context;
 
 struct r600_resource {
@@ -136,6 +150,7 @@ struct r600_common_screen {
 	enum radeon_family		family;
 	enum chip_class			chip_class;
 	struct radeon_info		info;
+	unsigned			debug_flags;
 };
 
 /* This encapsulates a state or an operation which can emitted into the GPU