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authorMarek Olšák <[email protected]>2015-01-04 22:16:53 +0100
committerMarek Olšák <[email protected]>2015-01-07 12:06:43 +0100
commit02ba7334d35cf8182048c17a149b16f18104c6bf (patch)
tree5a402674124cc421d1344b9f680a828eccba6c26 /src/gallium/drivers/radeon
parentedf18da85dd3b1865c4faaba650a8fa371b7103c (diff)
radeonsi: don't use TC L2 for updating descriptors on SI
It's causing problems, because we mix uncached CP DMA with cached WRITE_DATA when updating the same memory. The solution for SI is to use uncached access here, because CP DMA doesn't support cached access. CIK will be handled in the next patch. Reviewed-by: Michel Dänzer <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeon')
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