diff options
| author | Marek Olšák <[email protected]> | 2016-10-11 23:19:46 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2016-10-13 19:00:51 +0200 |
| commit | d4d9ec55c589156df4edc227a86b4a8c41048d58 (patch) | |
| tree | 646cdd6806f7a311c7e8a1403d5e715a79386af7 /src/gallium/drivers/radeon/radeon_winsys.h | |
| parent | a077185ea9d685967844b68aa09da6bd8aa430da (diff) | |
radeonsi: implement TC-compatible HTILE
so that decompress blits aren't needed and depth texturing needs less
memory bandwidth.
Z16 and Z24 are promoted to Z32_FLOAT by the driver, because TC-compatible
HTILE only supports Z32_FLOAT. This doubles memory footprint for Z16.
The format promotion is not visible to state trackers.
This is part of TC-compatible renderbuffer compression, which has 3 parts:
DCC, HTILE, FMASK. Only TC-compatible FMASK compression is missing now.
I don't see a measurable increase in performance though.
(I tested Talos Principle and DiRT: Showdown, the latter is improved by
0.5%, which is almost noise, and it originally used layered Z16,
so at least we know that Z16 promoted to Z32F isn't slower now)
Tested-by: Edmondo Tommasina <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeon/radeon_winsys.h')
| -rw-r--r-- | src/gallium/drivers/radeon/radeon_winsys.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h index 7146737c826..8946209d337 100644 --- a/src/gallium/drivers/radeon/radeon_winsys.h +++ b/src/gallium/drivers/radeon/radeon_winsys.h @@ -278,6 +278,7 @@ enum radeon_feature_id { #define RADEON_SURF_HAS_TILE_MODE_INDEX (1 << 20) #define RADEON_SURF_FMASK (1 << 21) #define RADEON_SURF_DISABLE_DCC (1 << 22) +#define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23) #define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK) #define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT) @@ -344,6 +345,9 @@ struct radeon_surf { uint64_t dcc_size; uint64_t dcc_alignment; + /* TC-compatible HTILE only. */ + uint64_t htile_size; + uint64_t htile_alignment; }; struct radeon_bo_list_item { |