radeonsi: use r600_common_context less pt7

Acked-by: Timothy Arceri <[email protected]>

1 files changed, 6 insertions, 8 deletions

diff --git a/src/gallium/drivers/radeon/radeon_video.c b/src/gallium/drivers/radeon/radeon_video.c
index d80410d51b3..3ae1d21cf1f 100644
--- a/src/gallium/drivers/radeon/radeon_video.c
+++ b/src/gallium/drivers/radeon/radeon_video.c
@@ -119,9 +119,9 @@ error:
 /* clear the buffer with zeros */
 void si_vid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffer)
 {
-	struct r600_common_context *rctx = (struct r600_common_context*)context;
+	struct si_context *sctx = (struct si_context*)context;
 
-	rctx->dma_clear_buffer(context, &buffer->res->b.b, 0,
+	sctx->b.dma_clear_buffer(context, &buffer->res->b.b, 0,
 			       buffer->res->buf->size, 0);
 	context->flush(context, NULL, 0);
 }
@@ -130,25 +130,23 @@ void si_vid_clear_buffer(struct pipe_context *context, struct rvid_buffer* buffe
  * join surfaces into the same buffer with identical tiling params
  * sumup their sizes and replace the backend buffers with a single bo
  */
-void si_vid_join_surfaces(struct r600_common_context *rctx,
+void si_vid_join_surfaces(struct si_context *sctx,
 			  struct pb_buffer** buffers[VL_NUM_COMPONENTS],
 			  struct radeon_surf *surfaces[VL_NUM_COMPONENTS])
 {
-	struct radeon_winsys* ws;
+	struct radeon_winsys *ws = sctx->b.ws;;
 	unsigned best_tiling, best_wh, off;
 	unsigned size, alignment;
 	struct pb_buffer *pb;
 	unsigned i, j;
 
-	ws = rctx->ws;
-
 	for (i = 0, best_tiling = 0, best_wh = ~0; i < VL_NUM_COMPONENTS; ++i) {
 		unsigned wh;
 
 		if (!surfaces[i])
 			continue;
 
-		if (rctx->chip_class < GFX9) {
+		if (sctx->b.chip_class < GFX9) {
 			/* choose the smallest bank w/h for now */
 			wh = surfaces[i]->u.legacy.bankw * surfaces[i]->u.legacy.bankh;
 			if (wh < best_wh) {
@@ -165,7 +163,7 @@ void si_vid_join_surfaces(struct r600_common_context *rctx,
 		/* adjust the texture layer offsets */
 		off = align(off, surfaces[i]->surf_alignment);
 
-		if (rctx->chip_class < GFX9) {
+		if (sctx->b.chip_class < GFX9) {
 			/* copy the tiling parameters */
 			surfaces[i]->u.legacy.bankw = surfaces[best_tiling]->u.legacy.bankw;
 			surfaces[i]->u.legacy.bankh = surfaces[best_tiling]->u.legacy.bankh;