diff options
| author | Dave Airlie <[email protected]> | 2015-07-01 04:58:24 +0100 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2015-07-12 22:40:51 +0100 |
| commit | 4cbf0a0ccf2fb4545b206066b756fd9a07acab92 (patch) | |
| tree | a4890fa9bc211304fe5a301bac972838e1bfc2a2 /src/gallium/drivers/radeon/radeon_llvm.h | |
| parent | 8108de4774f2542a8fe65de71b82221821f73434 (diff) | |
radeonsi: ARB_gpu_shader_fp64 + ARB_vertex_attrib_64bit support.
This adds the translation from TGSI to AMDGPU llvm backend, for the
64-bit opcodes. The backend pretty much handles everything for us
fine. There is one patch required for SI DFRAC support, that I know
off.
[airlied: fixed missing comma, updated relnotes]
Reviewed-by: Marek Olšák <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeon/radeon_llvm.h')
| -rw-r--r-- | src/gallium/drivers/radeon/radeon_llvm.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeon/radeon_llvm.h b/src/gallium/drivers/radeon/radeon_llvm.h index 6a9557b0b73..591e698d482 100644 --- a/src/gallium/drivers/radeon/radeon_llvm.h +++ b/src/gallium/drivers/radeon/radeon_llvm.h @@ -146,6 +146,8 @@ static inline LLVMTypeRef tgsi2llvmtype( case TGSI_TYPE_UNSIGNED: case TGSI_TYPE_SIGNED: return LLVMInt32TypeInContext(ctx); + case TGSI_TYPE_DOUBLE: + return LLVMDoubleTypeInContext(ctx); case TGSI_TYPE_UNTYPED: case TGSI_TYPE_FLOAT: return LLVMFloatTypeInContext(ctx); @@ -205,6 +207,9 @@ build_tgsi_intrinsic_nomem( struct lp_build_tgsi_context * bld_base, struct lp_build_emit_data * emit_data); - +LLVMValueRef +radeon_llvm_emit_fetch_double(struct lp_build_tgsi_context *bld_base, + LLVMValueRef ptr, + LLVMValueRef ptr2); #endif /* RADEON_LLVM_H */ |