diff options
author | Marek Olšák <[email protected]> | 2016-06-03 20:48:01 +0200 |
---|---|---|
committer | Marek Olšák <[email protected]> | 2016-06-08 00:22:45 +0200 |
commit | 00389100b63d03adf70892b721d1b2e8b8d5e48a (patch) | |
tree | 8d7d025d5fb201d23034dff287a0cd6a5531af03 /src/gallium/drivers/radeon/r600_texture.c | |
parent | c65361763cca709a28534aa354b6dffe1cbadf99 (diff) |
winsys/amdgpu: enable DCC for mipmapped textures
Also add dcc_fast_clear_size for clearing only the necessary subset
of DCC. For no AA, it's equal to the size of the whole DCC level.
Reviewed-by: Nicolai Hähnle <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeon/r600_texture.c')
-rw-r--r-- | src/gallium/drivers/radeon/r600_texture.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index 27b464fa509..9daad65a04c 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -931,8 +931,11 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f) rtex->dcc_offset, rtex->surface.dcc_size, rtex->surface.dcc_alignment); for (i = 0; i <= rtex->surface.last_level; i++) - fprintf(f, " DCCLevel[%i]: offset=%"PRIu64"\n", - i, rtex->surface.level[i].dcc_offset); + fprintf(f, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64", " + "fast_clear_size=%"PRIu64"\n", + i, rtex->surface.level[i].dcc_enabled, + rtex->surface.level[i].dcc_offset, + rtex->surface.level[i].dcc_fast_clear_size); } for (i = 0; i <= rtex->surface.last_level; i++) @@ -1865,7 +1868,8 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx, vi_get_fast_clear_parameters(fb->cbufs[i]->format, color, &reset_value, &clear_words_needed); rctx->clear_buffer(&rctx->b, &tex->resource.b.b, - tex->dcc_offset, tex->surface.dcc_size, + tex->dcc_offset, + tex->surface.level[0].dcc_fast_clear_size, reset_value, R600_COHERENCY_CB_META); if (clear_words_needed) |