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authorMarek Olšák <[email protected]>2015-12-09 20:26:21 +0100
committerMarek Olšák <[email protected]>2015-12-11 15:25:12 +0100
commitd3c08309abd17b6e0d466b677af57e3cc74b0e00 (patch)
treefad08b14200db265c76988dc490080d83770d49e /src/gallium/drivers/radeon/cayman_msaa.c
parent7c29bf26bbaa1ead489f3dd35a8458ba58d2195d (diff)
gallium/radeon: fix Hyper-Z hangs by programming PA_SC_MODE_CNTL_1 correctly
This is the recommended setting according to hw people and it makes Hyper-Z stable. Just the two magic states. This fixes Evergreen, Cayman, SI, CI, VI (using the Cayman code). Cc: 11.0 11.1 <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeon/cayman_msaa.c')
-rw-r--r--src/gallium/drivers/radeon/cayman_msaa.c12
1 files changed, 9 insertions, 3 deletions
diff --git a/src/gallium/drivers/radeon/cayman_msaa.c b/src/gallium/drivers/radeon/cayman_msaa.c
index c6afa8256db..81f41127af6 100644
--- a/src/gallium/drivers/radeon/cayman_msaa.c
+++ b/src/gallium/drivers/radeon/cayman_msaa.c
@@ -229,13 +229,17 @@ void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
- EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1));
+ EG_S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
+ EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
+ EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
} else if (overrast_samples > 1) {
radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
S_028804_STATIC_ANCHOR_ASSOCIATIONS(1) |
S_028804_OVERRASTERIZATION_AMOUNT(log_samples));
- radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, 0);
+ radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
+ EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
+ EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
}
} else {
radeon_set_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
@@ -245,6 +249,8 @@ void cayman_emit_msaa_config(struct radeon_winsys_cs *cs, int nr_samples,
radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
- radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1, 0);
+ radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
+ EG_S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
+ EG_S_028A4C_FORCE_EOV_REZ_ENABLE(1));
}
}