diff options
| author | Tom Stellard <[email protected]> | 2012-05-24 09:28:44 -0400 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-05-24 14:12:32 -0400 |
| commit | d088da917bb3495491b9a5da5ca1716ddd91ddd5 (patch) | |
| tree | 04e6db13a10f4eea63067429781fcb398cc0d915 /src/gallium/drivers/radeon/SIInstructions.td | |
| parent | 662ccbfc21a650e0a52f6d293fa33f9e23e654c6 (diff) | |
radeon/llvm: Remove auto-generated AMDIL->ISA conversion code
Diffstat (limited to 'src/gallium/drivers/radeon/SIInstructions.td')
| -rw-r--r-- | src/gallium/drivers/radeon/SIInstructions.td | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td index 1818e472c60..8505df9b0ce 100644 --- a/src/gallium/drivers/radeon/SIInstructions.td +++ b/src/gallium/drivers/radeon/SIInstructions.td @@ -12,7 +12,6 @@ def isSI : Predicate<"Subtarget.device()" "->getGeneration() == AMDILDeviceInfo::HD7XXX">; let Predicates = [isSI] in { -let Gen = AMDGPUGen.SI in { def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>; def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>; @@ -462,7 +461,7 @@ def IMAGE_SAMPLE : MIMG_Load_Helper <0x00000020, "IMAGE_SAMPLE">; //def V_NOP : VOP1_ <0x00000000, "V_NOP", []>; let neverHasSideEffects = 1 in { -defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", [], AMDILInst.MOVE_f32>; +defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>; } // End neverHasSideEffects defm V_READFIRSTLANE_B32 : VOP1_32 <0x00000002, "V_READFIRSTLANE_B32", []>; //defm V_CVT_I32_F64 : VOP1_32 <0x00000003, "V_CVT_I32_F64", []>; @@ -865,8 +864,6 @@ def VS_LOAD_BUFFER_INDEX : InstSI < } // end IsCodeGenOnly, isPseudo -} // end Gen = AMDGPUGen.SI - /* int_SI_vs_load_input */ def : Pat< (int_SI_vs_load_input SReg_64:$tlst_sgpr, IMM8bit:$t_offset, IMM12bit:$attr_offset, |