diff options
| author | Tom Stellard <[email protected]> | 2012-08-31 11:29:49 -0400 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-08-31 12:54:58 -0400 |
| commit | 022f6d88616bf5ea3903c5056d6147e9cf356aa9 (patch) | |
| tree | cd93db13aa7434b8b09d8900bec327906a27bfd1 /src/gallium/drivers/radeon/SIInstructions.td | |
| parent | 1cee70c5d836ee4c3981910ee46ed9d7471d39d8 (diff) | |
radeon/llvm: Rework how immediate operands are handled with SI
Immediate operands were previously handled in the CodeEmitter, but that
code was buggy and very confusing. This commit adds a pass that simplifies
the handling of immediate operands by spliting the loading of the
immediate into a sperate insruction that is bundled with the original.
Diffstat (limited to 'src/gallium/drivers/radeon/SIInstructions.td')
| -rw-r--r-- | src/gallium/drivers/radeon/SIInstructions.td | 27 |
1 files changed, 19 insertions, 8 deletions
diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td index 7802ec6cb54..291c03418a0 100644 --- a/src/gallium/drivers/radeon/SIInstructions.td +++ b/src/gallium/drivers/radeon/SIInstructions.td @@ -887,21 +887,21 @@ def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>; //def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>; def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>; -class V_MOV_IMM <Operand immType, SDNode immNode> : VOP1 < - 0x1, +class V_MOV_IMM <Operand immType, SDNode immNode> : InstSI < (outs VReg_32:$dst), (ins immType:$src0), "V_MOV_IMM", [(set VReg_32:$dst, (immNode:$src0))] >; +let isCodeGenOnly = 1, isPseudo = 1 in { + def V_MOV_IMM_I32 : V_MOV_IMM<i32imm, imm>; def V_MOV_IMM_F32 : V_MOV_IMM<f32imm, fpimm>; -def S_MOV_IMM_I32 : SOP1 < - 0x3, +def S_MOV_IMM_I32 : InstSI < (outs SReg_32:$dst), - (ins i32Literal:$src0), + (ins i32imm:$src0), "S_MOV_IMM_I32", [(set SReg_32:$dst, (imm:$src0))] >; @@ -910,14 +910,25 @@ def S_MOV_IMM_I32 : SOP1 < // type for indices on load and store instructions. The pattern for // S_MOV_IMM_I64 will only match i64 immediates that can fit into 32-bits, // which the hardware can handle. -def S_MOV_IMM_I64 : SOP1 < - 0x3, +def S_MOV_IMM_I64 : InstSI < (outs SReg_64:$dst), - (ins i64Literal:$src0), + (ins i64imm:$src0), "S_MOV_IMM_I64 $dst, $src0", [(set SReg_64:$dst, (IMM32bitIn64bit:$src0))] >; +} // End isCodeGenOnly, isPseudo = 1 + +class SI_LOAD_LITERAL<Operand ImmType> : + Enc32 <(outs), (ins ImmType:$imm), "LOAD_LITERAL $imm", []> { + + bits<32> imm; + let Inst{31-0} = imm; +} + +def SI_LOAD_LITERAL_I32 : SI_LOAD_LITERAL<i32imm>; +def SI_LOAD_LITERAL_F32 : SI_LOAD_LITERAL<f32imm>; + let isCodeGenOnly = 1, isPseudo = 1 in { def SET_M0 : InstSI < |