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authorTom Stellard <[email protected]>2012-09-11 15:24:32 -0400
committerTom Stellard <[email protected]>2012-09-13 10:38:02 -0400
commit6a5a4d59ce63aa1fa14d3dd6c50169c532424b6d (patch)
treeba0e1c5952a7969ae30fdf3be6c7d90bf2c73778 /src/gallium/drivers/radeon/SIInstructions.td
parent70a50685a8f7934e23978ac34dcefcfab46c69de (diff)
radeon/llvm: Fix lowering of vbuild
Some of the old AMDIL code was hard-coding subreg indices when creating the VBUILD node, which was making it difficult to match the vector_insert patterns.
Diffstat (limited to 'src/gallium/drivers/radeon/SIInstructions.td')
-rw-r--r--src/gallium/drivers/radeon/SIInstructions.td4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeon/SIInstructions.td b/src/gallium/drivers/radeon/SIInstructions.td
index 1f3b92de6b3..05665629428 100644
--- a/src/gallium/drivers/radeon/SIInstructions.td
+++ b/src/gallium/drivers/radeon/SIInstructions.td
@@ -1058,8 +1058,8 @@ def : Insert_Element <f32, v4f32, VReg_32, VReg_128, 5, sel_y>;
def : Insert_Element <f32, v4f32, VReg_32, VReg_128, 6, sel_z>;
def : Insert_Element <f32, v4f32, VReg_32, VReg_128, 7, sel_w>;
-def : Vector_Build <v4f32, VReg_32>;
-def : Vector_Build <v4i32, SReg_32>;
+def : Vector_Build <v4f32, VReg_128, f32, VReg_32>;
+def : Vector_Build <v4i32, SReg_128, i32, SReg_32>;
def : BitConvert <i32, f32, SReg_32>;
def : BitConvert <i32, f32, VReg_32>;