diff options
| author | Tom Stellard <[email protected]> | 2012-07-08 12:41:05 -0400 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-07-09 13:43:11 +0000 |
| commit | 76b44034b9b234d3db4012342f0fae677d4f10f6 (patch) | |
| tree | bac085be50fa71417aaf8533e614b3deacc1db4f /src/gallium/drivers/radeon/SIInstrInfo.cpp | |
| parent | 39323e8f792a33f4fe3028c286a1638dc16a38a4 (diff) | |
radeon/llvm: Rename namespace from AMDIL to AMDGPU
Diffstat (limited to 'src/gallium/drivers/radeon/SIInstrInfo.cpp')
| -rw-r--r-- | src/gallium/drivers/radeon/SIInstrInfo.cpp | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/gallium/drivers/radeon/SIInstrInfo.cpp b/src/gallium/drivers/radeon/SIInstrInfo.cpp index 1d464fec033..4438d67f877 100644 --- a/src/gallium/drivers/radeon/SIInstrInfo.cpp +++ b/src/gallium/drivers/radeon/SIInstrInfo.cpp @@ -38,7 +38,7 @@ SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB, unsigned DestReg, unsigned SrcReg, bool KillSrc) const { - BuildMI(MBB, MI, DL, get(AMDIL::V_MOV_B32_e32), DestReg) + BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg) .addReg(SrcReg, getKillRegState(KillSrc)); } @@ -59,7 +59,7 @@ unsigned SIInstrInfo::getEncodingBytes(const MachineInstr &MI) const } /* This instruction always has a literal */ - if (MI.getOpcode() == AMDIL::S_MOV_IMM_I32) { + if (MI.getOpcode() == AMDGPU::S_MOV_IMM_I32) { return 8; } @@ -80,7 +80,7 @@ unsigned SIInstrInfo::getEncodingBytes(const MachineInstr &MI) const MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg, int64_t Imm) const { - MachineInstr * MI = MF->CreateMachineInstr(get(AMDIL::V_MOV_IMM_I32), DebugLoc()); + MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_IMM_I32), DebugLoc()); MachineInstrBuilder(MI).addReg(DstReg, RegState::Define); MachineInstrBuilder(MI).addImm(Imm); @@ -92,13 +92,13 @@ bool SIInstrInfo::isMov(unsigned Opcode) const { switch(Opcode) { default: return false; - case AMDIL::S_MOV_B32: - case AMDIL::S_MOV_B64: - case AMDIL::V_MOV_B32_e32: - case AMDIL::V_MOV_B32_e64: - case AMDIL::V_MOV_IMM_F32: - case AMDIL::V_MOV_IMM_I32: - case AMDIL::S_MOV_IMM_I32: + case AMDGPU::S_MOV_B32: + case AMDGPU::S_MOV_B64: + case AMDGPU::V_MOV_B32_e32: + case AMDGPU::V_MOV_B32_e64: + case AMDGPU::V_MOV_IMM_F32: + case AMDGPU::V_MOV_IMM_I32: + case AMDGPU::S_MOV_IMM_I32: return true; } } |