diff options
| author | Tom Stellard <[email protected]> | 2012-07-25 08:30:32 -0400 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-07-27 17:08:08 +0000 |
| commit | 50ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48 (patch) | |
| tree | acc1b4b0a305aff1f771399445614bf10302fd24 /src/gallium/drivers/radeon/SIInstrFormats.td | |
| parent | c424975572af2edd46863e5bb9fe3c51c96b4f9b (diff) | |
radeon/llvm: Add special nodes for SALU operations on VCC
The VCC register is tricky because the SALU views it as 64-bit, but the
VALU views it as 1-bit. In order to deal with this we've added some
special bitcast and binary operations to help convert from the 64-bit
SALU view to the 1-bit VALU view and vice versa.
Diffstat (limited to 'src/gallium/drivers/radeon/SIInstrFormats.td')
| -rw-r--r-- | src/gallium/drivers/radeon/SIInstrFormats.td | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/SIInstrFormats.td b/src/gallium/drivers/radeon/SIInstrFormats.td index 79f47087ce7..3d9d47489d7 100644 --- a/src/gallium/drivers/radeon/SIInstrFormats.td +++ b/src/gallium/drivers/radeon/SIInstrFormats.td @@ -41,6 +41,9 @@ class SOP2_32 <bits<7> op, string opName, list<dag> pattern> class SOP2_64 <bits<7> op, string opName, list<dag> pattern> : SOP2 <op, (outs SReg_64:$dst), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>; +class SOP2_VCC <bits<7> op, string opName, list<dag> pattern> + : SOP2 <op, (outs VCCReg:$vcc), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>; + class VOP1_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc, string opName, list<dag> pattern> : VOP1 < |