diff options
| author | Tom Stellard <[email protected]> | 2012-07-25 08:30:32 -0400 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-07-27 17:08:08 +0000 |
| commit | 50ff2dc0a4f553eb8d634d6f081fe5e4e25f6f48 (patch) | |
| tree | acc1b4b0a305aff1f771399445614bf10302fd24 /src/gallium/drivers/radeon/SIISelLowering.h | |
| parent | c424975572af2edd46863e5bb9fe3c51c96b4f9b (diff) | |
radeon/llvm: Add special nodes for SALU operations on VCC
The VCC register is tricky because the SALU views it as 64-bit, but the
VALU views it as 1-bit. In order to deal with this we've added some
special bitcast and binary operations to help convert from the 64-bit
SALU view to the 1-bit VALU view and vice versa.
Diffstat (limited to 'src/gallium/drivers/radeon/SIISelLowering.h')
| -rw-r--r-- | src/gallium/drivers/radeon/SIISelLowering.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/SIISelLowering.h b/src/gallium/drivers/radeon/SIISelLowering.h index f16202abcc5..10123e7b732 100644 --- a/src/gallium/drivers/radeon/SIISelLowering.h +++ b/src/gallium/drivers/radeon/SIISelLowering.h @@ -38,6 +38,8 @@ class SITargetLowering : public AMDGPUTargetLowering void lowerUSE_SGPR(MachineInstr *MI, MachineFunction * MF, MachineRegisterInfo & MRI) const; + SDValue Loweri1ContextSwitch(SDValue Op, SelectionDAG &DAG, + unsigned VCCNode) const; SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const; @@ -47,6 +49,7 @@ public: MachineBasicBlock * BB) const; virtual EVT getSetCCResultType(EVT VT) const; virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; + virtual const char* getTargetNodeName(unsigned Opcode) const; }; } // End namespace llvm |