diff options
| author | Tom Stellard <[email protected]> | 2012-08-20 21:08:03 +0000 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-08-21 15:42:44 +0000 |
| commit | 05882985757e655f5298af483c881008d45e6249 (patch) | |
| tree | ac1ed3f0b9ff0f55f23e34fb7a2d0e5596f707a9 /src/gallium/drivers/radeon/R600RegisterInfo.cpp | |
| parent | 1a25ebe3ce95a6a4aef7c844dbe95909976b68da (diff) | |
radeon/llvm: Add helper function for getting sub reg indices
Diffstat (limited to 'src/gallium/drivers/radeon/R600RegisterInfo.cpp')
| -rw-r--r-- | src/gallium/drivers/radeon/R600RegisterInfo.cpp | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/R600RegisterInfo.cpp b/src/gallium/drivers/radeon/R600RegisterInfo.cpp index 94752410bfb..c2e40c7214a 100644 --- a/src/gallium/drivers/radeon/R600RegisterInfo.cpp +++ b/src/gallium/drivers/radeon/R600RegisterInfo.cpp @@ -112,4 +112,16 @@ const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass( case MVT::i32: return AMDGPU::R600_TReg32RegisterClass; } } + +unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) const +{ + switch (Channel) { + default: assert(!"Invalid channel index"); return 0; + case 0: return AMDGPU::sel_x; + case 1: return AMDGPU::sel_y; + case 2: return AMDGPU::sel_z; + case 3: return AMDGPU::sel_w; + } +} + #include "R600HwRegInfo.include" |