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authorTom Stellard <[email protected]>2012-05-23 14:48:36 -0400
committerTom Stellard <[email protected]>2012-05-24 14:12:31 -0400
commit1404e6b9fcc6ff4f962cafa8d81226dff5fef54d (patch)
tree6b95f8c77c2aca771f75f490e46f61e2a597bcd3 /src/gallium/drivers/radeon/R600LowerInstructions.cpp
parent3059c075a73aa275cc43cf72ba87d64f6d748cd6 (diff)
radeon/llvm: Remove AMDIL binary instrutions (OR, AND, XOR, NOT)
Diffstat (limited to 'src/gallium/drivers/radeon/R600LowerInstructions.cpp')
-rw-r--r--src/gallium/drivers/radeon/R600LowerInstructions.cpp16
1 files changed, 0 insertions, 16 deletions
diff --git a/src/gallium/drivers/radeon/R600LowerInstructions.cpp b/src/gallium/drivers/radeon/R600LowerInstructions.cpp
index a5f57cc1d36..75113683032 100644
--- a/src/gallium/drivers/radeon/R600LowerInstructions.cpp
+++ b/src/gallium/drivers/radeon/R600LowerInstructions.cpp
@@ -98,22 +98,6 @@ bool R600LowerInstructionsPass::runOnMachineFunction(MachineFunction &MF)
.addOperand(MI.getOperand(1));
break;
- case AMDIL::BINARY_OR_f32:
- {
- unsigned tmp0 = MRI->createVirtualRegister(&AMDIL::GPRI32RegClass);
- BuildMI(MBB, I, MBB.findDebugLoc(I), TM.getInstrInfo()->get(AMDIL::FTOI), tmp0)
- .addOperand(MI.getOperand(1));
- unsigned tmp1 = MRI->createVirtualRegister(&AMDIL::GPRI32RegClass);
- BuildMI(MBB, I, MBB.findDebugLoc(I), TM.getInstrInfo()->get(AMDIL::FTOI), tmp1)
- .addOperand(MI.getOperand(2));
- unsigned tmp2 = MRI->createVirtualRegister(&AMDIL::GPRI32RegClass);
- BuildMI(MBB, I, MBB.findDebugLoc(I), TM.getInstrInfo()->get(AMDIL::BINARY_OR_i32), tmp2)
- .addReg(tmp0)
- .addReg(tmp1);
- BuildMI(MBB, I, MBB.findDebugLoc(I), TM.getInstrInfo()->get(AMDIL::ITOF), MI.getOperand(0).getReg())
- .addReg(tmp2);
- break;
- }
case AMDIL::CLAMP_f32:
{
MachineOperand lowOp = MI.getOperand(2);