diff options
| author | Vincent Lejeune <[email protected]> | 2012-09-24 16:04:26 +0200 |
|---|---|---|
| committer | Vincent Lejeune <[email protected]> | 2012-09-27 01:43:35 +0200 |
| commit | ff947c6d65830b7be6e9fcbfe666fa7dba6341f6 (patch) | |
| tree | 96de8c46afa7c97dc31589942e9cdc77238cfe51 /src/gallium/drivers/radeon/R600Instructions.td | |
| parent | bb7ecb29fb6358a4c65278c2fe88936c578074cd (diff) | |
radeon/llvm: improve select_cc lowering to generate CND* more often
v2: - Simplify isZero()
- Remove a unused function prototype
- Clean whitespace trails
Reviewed-by: Tom Stellard <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeon/R600Instructions.td')
| -rw-r--r-- | src/gallium/drivers/radeon/R600Instructions.td | 38 |
1 files changed, 32 insertions, 6 deletions
diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td index feb97fac822..1689a2f4ab8 100644 --- a/src/gallium/drivers/radeon/R600Instructions.td +++ b/src/gallium/drivers/radeon/R600Instructions.td @@ -545,7 +545,25 @@ def SETGE_UINT : R600_2OP < def CNDE_INT : R600_3OP < 0x1C, "CNDE_INT", [(set (i32 R600_Reg32:$dst), - (select R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))] + (selectcc (i32 R600_Reg32:$src0), 0, + (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2), + COND_EQ))] +>; + +def CNDGE_INT : R600_3OP < + 0x1E, "CNDGE_INT", + [(set (i32 R600_Reg32:$dst), + (selectcc (i32 R600_Reg32:$src0), 0, + (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2), + COND_GE))] +>; + +def CNDGT_INT : R600_3OP < + 0x1D, "CNDGT_INT", + [(set (i32 R600_Reg32:$dst), + (selectcc (i32 R600_Reg32:$src0), 0, + (i32 R600_Reg32:$src1), (i32 R600_Reg32:$src2), + COND_GT))] >; //===----------------------------------------------------------------------===// @@ -642,18 +660,26 @@ class MULADD_Common <bits<11> inst> : R600_3OP < class CNDE_Common <bits<11> inst> : R600_3OP < inst, "CNDE", - [(set (f32 R600_Reg32:$dst), - (select (i32 (fp_to_sint (fneg R600_Reg32:$src0))), (f32 R600_Reg32:$src2), (f32 R600_Reg32:$src1)))] + [(set R600_Reg32:$dst, + (selectcc (f32 R600_Reg32:$src0), FP_ZERO, + (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2), + COND_EQ))] >; class CNDGT_Common <bits<11> inst> : R600_3OP < inst, "CNDGT", - [] + [(set R600_Reg32:$dst, + (selectcc (f32 R600_Reg32:$src0), FP_ZERO, + (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2), + COND_GT))] >; - + class CNDGE_Common <bits<11> inst> : R600_3OP < inst, "CNDGE", - [(set R600_Reg32:$dst, (int_AMDGPU_cndlt R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))] + [(set R600_Reg32:$dst, + (selectcc (f32 R600_Reg32:$src0), FP_ZERO, + (f32 R600_Reg32:$src1), (f32 R600_Reg32:$src2), + COND_GE))] >; class DOT4_Common <bits<11> inst> : R600_REDUCTION < |