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authorVincent Lejeune <[email protected]>2012-08-01 22:49:42 +0200
committerTom Stellard <[email protected]>2012-08-15 21:07:14 +0000
commit0eca5fd919b0a31ea926b5f5072e5e56f7a55269 (patch)
treec0b8c89ee5bd21f84299dc7572a85dc04e80e45e /src/gallium/drivers/radeon/R600InstrInfo.h
parent6db2e9fdb0a35e27e6fc86a1485918b78717a425 (diff)
radeon/llvm: Lower branch/branch_cond into predicated jump
Signed-off-by: Tom Stellard <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeon/R600InstrInfo.h')
-rw-r--r--src/gallium/drivers/radeon/R600InstrInfo.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/R600InstrInfo.h b/src/gallium/drivers/radeon/R600InstrInfo.h
index 9bdda7a1e13..2819b0b87a2 100644
--- a/src/gallium/drivers/radeon/R600InstrInfo.h
+++ b/src/gallium/drivers/radeon/R600InstrInfo.h
@@ -34,6 +34,8 @@ namespace llvm {
const R600RegisterInfo RI;
AMDGPUTargetMachine &TM;
+ int getBranchInstr(const MachineOperand &op) const;
+
public:
explicit R600InstrInfo(AMDGPUTargetMachine &tm);
@@ -62,6 +64,13 @@ namespace llvm {
DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
const ScheduleDAG *DAG) const;
+ bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
+ SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
+
+ unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
+
+ unsigned RemoveBranch(MachineBasicBlock &MBB) const;
+
bool isPredicated(const MachineInstr *MI) const;
bool isPredicable(MachineInstr *MI) const;