diff options
| author | Tom Stellard <[email protected]> | 2012-06-05 20:10:31 -0400 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-06-06 13:46:04 -0400 |
| commit | d4942eb9fa1247053619be2b1e5a1b79f35c535d (patch) | |
| tree | dbc234aba08f848d97a4be6b7b680df932fd486b /src/gallium/drivers/radeon/R600InstrInfo.cpp | |
| parent | edceed1b9a46c4a92a6113e8b1c5d2433568143d (diff) | |
radeon/llvm: Remove obselete hooks for the ConvertToISA pass
We can't remove this pass yet, because we need it to convert AMDIL
registers in BRANCH* instructions, but we don't need it for
instruction conversion any more.
Diffstat (limited to 'src/gallium/drivers/radeon/R600InstrInfo.cpp')
| -rw-r--r-- | src/gallium/drivers/radeon/R600InstrInfo.cpp | 40 |
1 files changed, 0 insertions, 40 deletions
diff --git a/src/gallium/drivers/radeon/R600InstrInfo.cpp b/src/gallium/drivers/radeon/R600InstrInfo.cpp index 363c8148863..3d65e7373c9 100644 --- a/src/gallium/drivers/radeon/R600InstrInfo.cpp +++ b/src/gallium/drivers/radeon/R600InstrInfo.cpp @@ -61,46 +61,6 @@ R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB, } } -unsigned R600InstrInfo::getISAOpcode(unsigned opcode) const -{ - switch (opcode) { - default: return opcode; - case AMDIL::IEQ: - return AMDIL::SETE_INT; - case AMDIL::INE: - return AMDIL::SETNE_INT; - case AMDIL::IGE: - return AMDIL::SETGE_INT; - case AMDIL::MOVE_f32: - case AMDIL::MOVE_i32: - return AMDIL::MOV; - case AMDIL::UGE: - return AMDIL::SETGE_UINT; - case AMDIL::UGT: - return AMDIL::SETGT_UINT; - } -} - -unsigned R600InstrInfo::getASHRop() const -{ - unsigned gen = TM.getSubtarget<AMDILSubtarget>().device()->getGeneration(); - if (gen < AMDILDeviceInfo::HD5XXX) { - return AMDIL::ASHR_r600; - } else { - return AMDIL::ASHR_eg; - } -} - -unsigned R600InstrInfo::getLSHRop() const -{ - unsigned gen = TM.getSubtarget<AMDILSubtarget>().device()->getGeneration(); - if (gen < AMDILDeviceInfo::HD5XXX) { - return AMDIL::LSHR_r600; - } else { - return AMDIL::LSHR_eg; - } -} - MachineInstr * R600InstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg, int64_t Imm) const { |