diff options
| author | Tom Stellard <[email protected]> | 2012-08-22 15:04:58 +0000 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-08-23 15:00:47 +0000 |
| commit | 67a47a445b544ac638d10303dc697d70f25d12fb (patch) | |
| tree | 53389276cfde310b51178027f9b684a344f598da /src/gallium/drivers/radeon/R600InstrInfo.cpp | |
| parent | 3a7a56e7aa56bc6cb847c241ef6bd749713ae6e1 (diff) | |
radeon/llvm: Add flag operand to some instructions
This new operand replaces the MachineOperand flags in LLVM, which
will be deprecated soon. Eventually all instructions should have a flag
operand, but for now this operand has only been added to instructions
that need it.
Diffstat (limited to 'src/gallium/drivers/radeon/R600InstrInfo.cpp')
| -rw-r--r-- | src/gallium/drivers/radeon/R600InstrInfo.cpp | 30 |
1 files changed, 28 insertions, 2 deletions
diff --git a/src/gallium/drivers/radeon/R600InstrInfo.cpp b/src/gallium/drivers/radeon/R600InstrInfo.cpp index 2b6ce4be36f..4cca8ebfea7 100644 --- a/src/gallium/drivers/radeon/R600InstrInfo.cpp +++ b/src/gallium/drivers/radeon/R600InstrInfo.cpp @@ -57,6 +57,7 @@ R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB, BuildMI(MBB, MI, DL, get(AMDGPU::MOV)) .addReg(RI.getSubReg(DestReg, SubRegIndex), RegState::Define) .addReg(RI.getSubReg(SrcReg, SubRegIndex)) + .addImm(0) // Flag .addReg(0) // PREDICATE_BIT .addReg(DestReg, RegState::Define | RegState::Implicit); } @@ -68,6 +69,7 @@ R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB, BuildMI(MBB, MI, DL, get(AMDGPU::MOV), DestReg) .addReg(SrcReg, getKillRegState(KillSrc)) + .addImm(0) // Flag .addReg(0); // PREDICATE_BIT } } @@ -520,11 +522,35 @@ int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData, } //===----------------------------------------------------------------------===// -// Instruction flag setters +// Instruction flag getters/setters //===----------------------------------------------------------------------===// +#define GET_FLAG_OPERAND_IDX(MI) (((MI).getDesc().TSFlags >> 7) & 0x3) + +bool R600InstrInfo::HasFlagOperand(const MachineInstr &MI) const +{ + return GET_FLAG_OPERAND_IDX(MI) != 0; +} + void R600InstrInfo::AddFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const { - MI->getOperand(Operand).addTargetFlag(Flag); + unsigned FlagIndex = GET_FLAG_OPERAND_IDX(*MI); + assert(FlagIndex != 0 && + "Instruction flags not supported for this instruction"); + MachineOperand &FlagOp = MI->getOperand(FlagIndex); + assert(FlagOp.isImm()); + FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand))); +} + +bool R600InstrInfo::IsFlagSet(const MachineInstr &MI, unsigned Operand, + unsigned Flag) const +{ + unsigned FlagIndex = GET_FLAG_OPERAND_IDX(MI); + if (FlagIndex == 0) { + return false; + } + assert(MI.getOperand(FlagIndex).isImm()); + return !!((MI.getOperand(FlagIndex).getImm() >> + (NUM_MO_FLAGS * Operand)) & Flag); } |