diff options
| author | Tom Stellard <[email protected]> | 2012-08-23 21:00:13 +0000 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-08-23 21:54:32 +0000 |
| commit | 2ad8608cb3e6a8d2f375ad2295504167b082711f (patch) | |
| tree | 6b84323bc2bd123483f556c749d5fa5b63f8242a /src/gallium/drivers/radeon/R600ISelLowering.cpp | |
| parent | 228a6641ccddaf24a993f827af1e97379785985a (diff) | |
radeon/llvm: Fix some coding style issues
Diffstat (limited to 'src/gallium/drivers/radeon/R600ISelLowering.cpp')
| -rw-r--r-- | src/gallium/drivers/radeon/R600ISelLowering.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp index f96887c0edb..afa80c5c4dc 100644 --- a/src/gallium/drivers/radeon/R600ISelLowering.cpp +++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp @@ -67,7 +67,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter( .addOperand(MI->getOperand(1)) .addImm(0) // Flags .addReg(AMDGPU::PRED_SEL_OFF); - TII->AddFlag(NewMI, 0, MO_FLAG_CLAMP); + TII->addFlag(NewMI, 0, MO_FLAG_CLAMP); break; } case AMDGPU::FABS_R600: @@ -78,7 +78,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter( .addOperand(MI->getOperand(1)) .addImm(0) // Flags .addReg(AMDGPU::PRED_SEL_OFF); - TII->AddFlag(NewMI, 1, MO_FLAG_ABS); + TII->addFlag(NewMI, 1, MO_FLAG_ABS); break; } @@ -90,7 +90,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter( .addOperand(MI->getOperand(1)) .addImm(0) // Flags .addReg(AMDGPU::PRED_SEL_OFF); - TII->AddFlag(NewMI, 1, MO_FLAG_NEG); + TII->addFlag(NewMI, 1, MO_FLAG_NEG); break; } @@ -109,7 +109,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter( unsigned maskedRegister = MI->getOperand(0).getReg(); assert(TargetRegisterInfo::isVirtualRegister(maskedRegister)); MachineInstr * defInstr = MRI.getVRegDef(maskedRegister); - TII->AddFlag(defInstr, 0, MO_FLAG_MASK); + TII->addFlag(defInstr, 0, MO_FLAG_MASK); // Return early so the instruction is not erased return BB; } @@ -206,7 +206,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter( .addOperand(MI->getOperand(1)) .addImm(OPCODE_IS_ZERO) .addImm(0); // Flags - TII->AddFlag(NewMI, 1, MO_FLAG_PUSH); + TII->addFlag(NewMI, 1, MO_FLAG_PUSH); BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP)) .addOperand(MI->getOperand(0)) .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); @@ -220,7 +220,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter( .addOperand(MI->getOperand(1)) .addImm(OPCODE_IS_ZERO_INT) .addImm(0); // Flags - TII->AddFlag(NewMI, 1, MO_FLAG_PUSH); + TII->addFlag(NewMI, 1, MO_FLAG_PUSH); BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP)) .addOperand(MI->getOperand(0)) .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill); |