diff options
author | Vadim Girlin <[email protected]> | 2012-05-15 18:53:06 +0400 |
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committer | Vadim Girlin <[email protected]> | 2012-05-15 18:53:06 +0400 |
commit | fa5a963dd6c2622c416d53e49b08c4b3cbce7483 (patch) | |
tree | 57d3fdfb66c953c1cbfffe8642cf4b478b22aa90 /src/gallium/drivers/radeon/R600ISelLowering.cpp | |
parent | b655f78b25454e00f4300fb5ccd35b3d0ab8a740 (diff) |
radeon/llvm: add SET_GRADIENTS*, fix SAMPLE_G
Signed-off-by: Vadim Girlin <[email protected]>
Reviewed-by: Tom Stellard <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeon/R600ISelLowering.cpp')
-rw-r--r-- | src/gallium/drivers/radeon/R600ISelLowering.cpp | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp index e85ac31b34c..4db40f799ed 100644 --- a/src/gallium/drivers/radeon/R600ISelLowering.cpp +++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp @@ -131,6 +131,53 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter( MFI->ReservedRegs.push_back(ReservedReg); break; } + + case AMDIL::TXD: + { + unsigned t0 = MRI.createVirtualRegister(AMDIL::R600_Reg128RegisterClass); + unsigned t1 = MRI.createVirtualRegister(AMDIL::R600_Reg128RegisterClass); + + BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDIL::TEX_SET_GRADIENTS_H), t0) + .addOperand(MI->getOperand(3)) + .addOperand(MI->getOperand(4)) + .addOperand(MI->getOperand(5)); + BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDIL::TEX_SET_GRADIENTS_V), t1) + .addOperand(MI->getOperand(2)) + .addOperand(MI->getOperand(4)) + .addOperand(MI->getOperand(5)); + BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDIL::TEX_SAMPLE_G)) + .addOperand(MI->getOperand(0)) + .addOperand(MI->getOperand(1)) + .addOperand(MI->getOperand(4)) + .addOperand(MI->getOperand(5)) + .addReg(t0, RegState::Implicit) + .addReg(t1, RegState::Implicit); + break; + } + case AMDIL::TXD_SHADOW: + { + unsigned t0 = MRI.createVirtualRegister(AMDIL::R600_Reg128RegisterClass); + unsigned t1 = MRI.createVirtualRegister(AMDIL::R600_Reg128RegisterClass); + + BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDIL::TEX_SET_GRADIENTS_H), t0) + .addOperand(MI->getOperand(3)) + .addOperand(MI->getOperand(4)) + .addOperand(MI->getOperand(5)); + BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDIL::TEX_SET_GRADIENTS_V), t1) + .addOperand(MI->getOperand(2)) + .addOperand(MI->getOperand(4)) + .addOperand(MI->getOperand(5)); + BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDIL::TEX_SAMPLE_C_G)) + .addOperand(MI->getOperand(0)) + .addOperand(MI->getOperand(1)) + .addOperand(MI->getOperand(4)) + .addOperand(MI->getOperand(5)) + .addReg(t0, RegState::Implicit) + .addReg(t1, RegState::Implicit); + break; + } + + } MI->eraseFromParent(); |