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authorTom Stellard <[email protected]>2012-05-25 12:53:22 -0400
committerTom Stellard <[email protected]>2012-05-25 15:40:59 -0400
commit704eac09166aa6dc4c1aa82f8d0938c4060e51f4 (patch)
tree4c9b9202563a964d6d6710c5ef3cca2c7c96be94 /src/gallium/drivers/radeon/R600ISelLowering.cpp
parent4863477e22e02af046915ca2a33dbecfd0ed34b4 (diff)
radeon/llvm: Use a custom inserter for MASK_WRITE
Diffstat (limited to 'src/gallium/drivers/radeon/R600ISelLowering.cpp')
-rw-r--r--src/gallium/drivers/radeon/R600ISelLowering.cpp12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp
index de60a2d0e59..77d90e21d1b 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.cpp
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -139,6 +139,18 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
AMDIL::R600_TReg32RegClass.getRegister(RegIndex));
break;
}
+
+ case AMDIL::MASK_WRITE:
+ {
+ unsigned maskedRegister = MI->getOperand(0).getReg();
+ assert(TargetRegisterInfo::isVirtualRegister(maskedRegister));
+ MachineInstr * defInstr = MRI.getVRegDef(maskedRegister);
+ MachineOperand * def = defInstr->findRegisterDefOperand(maskedRegister);
+ def->addTargetFlag(MO_FLAG_MASK);
+ // Return early so the instruction is not erased
+ return BB;
+ }
+
case AMDIL::STORE_OUTPUT:
{
int64_t OutputIndex = MI->getOperand(1).getImm();