diff options
| author | Tom Stellard <[email protected]> | 2012-07-10 11:15:49 -0400 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-07-11 17:47:20 +0000 |
| commit | 49ae102ee346d4be6a61ebdaba6e5d5ad8469407 (patch) | |
| tree | 069e17b22b82de1661c1f81cb1e08a80ec507d28 /src/gallium/drivers/radeon/R600ISelLowering.cpp | |
| parent | bbdf3af8577ca61fc54c4a1615e80940c904636e (diff) | |
radeon/llvm: Use multiclasses for floating point loads
The original strategy for handling floating point loads, which was to
lower (f32 load) to (f32 bitcast (i32 load)) wasn't really working. The
main problem was that the DAG legalizer couldn't handle replacing a node
with two results (load) with a node with only one result (bitcast).
Diffstat (limited to 'src/gallium/drivers/radeon/R600ISelLowering.cpp')
| -rw-r--r-- | src/gallium/drivers/radeon/R600ISelLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp index 00ab7519dd6..ee4fea88f5f 100644 --- a/src/gallium/drivers/radeon/R600ISelLowering.cpp +++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp @@ -253,7 +253,7 @@ void R600TargetLowering::lowerImplicitParameter(MachineInstr *MI, MachineBasicBl .addReg(AMDGPU::ALU_LITERAL_X) .addImm(dword_offset * 4); - BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::VTX_READ_PARAM_eg)) + BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::VTX_READ_PARAM_i32_eg)) .addOperand(MI->getOperand(0)) .addReg(PtrReg) .addImm(0); |