diff options
| author | Tom Stellard <[email protected]> | 2012-08-23 21:51:48 +0000 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-08-23 21:54:32 +0000 |
| commit | 1434a86f50e4ffc69316c7e948ebfe56a25d31da (patch) | |
| tree | 1a15b48943350379145227139f16d478696fcb5c /src/gallium/drivers/radeon/R600ISelLowering.cpp | |
| parent | 1bd7b29a661a336dbc96c160197c739657991ef3 (diff) | |
radeon/llvm: Set End of Program bit on RAT instructions
This code was accidently dropped during the MCCodeEmitter conversion.
Diffstat (limited to 'src/gallium/drivers/radeon/R600ISelLowering.cpp')
| -rw-r--r-- | src/gallium/drivers/radeon/R600ISelLowering.cpp | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp index 376ac70c62c..fec9d4e257c 100644 --- a/src/gallium/drivers/radeon/R600ISelLowering.cpp +++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp @@ -121,6 +121,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter( &AMDGPU::R600_TReg32_XRegClass); unsigned ShiftValue = MRI.createVirtualRegister( &AMDGPU::R600_TReg32RegClass); + unsigned EOP = (llvm::next(I)->getOpcode() == AMDGPU::RETURN) ? 1 : 0; // XXX In theory, we should be able to pass ShiftValue directly to // the LSHR_eg instruction as an inline literal, but I tried doing it @@ -136,7 +137,8 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter( .addReg(AMDGPU::PRED_SEL_OFF); BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(MI->getOpcode())) .addOperand(MI->getOperand(0)) - .addReg(NewAddr); + .addReg(NewAddr) + .addImm(EOP); // Set End of program bit break; } |