diff options
| author | Vincent Lejeune <[email protected]> | 2012-08-01 22:49:40 +0200 |
|---|---|---|
| committer | Tom Stellard <[email protected]> | 2012-08-15 21:07:13 +0000 |
| commit | 8263408a91b6b3beb5af5de6bdc7e5d13197a268 (patch) | |
| tree | 22f874d9ff229145abf992e2bfbd022bde656e20 /src/gallium/drivers/radeon/R600GenRegisterInfo.pl | |
| parent | 8f597d57e959830040473b548e0e04cfc63866c2 (diff) | |
radeon/llvm: Support for predicate bit
Tom Stellard:
- A few changes to predicate register defs
Signed-off-by: Tom Stellard <[email protected]>
Diffstat (limited to 'src/gallium/drivers/radeon/R600GenRegisterInfo.pl')
| -rw-r--r-- | src/gallium/drivers/radeon/R600GenRegisterInfo.pl | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeon/R600GenRegisterInfo.pl b/src/gallium/drivers/radeon/R600GenRegisterInfo.pl index 6bbe21c5f0a..a28a3ad1d93 100644 --- a/src/gallium/drivers/radeon/R600GenRegisterInfo.pl +++ b/src/gallium/drivers/radeon/R600GenRegisterInfo.pl @@ -69,6 +69,10 @@ def NEG_HALF : R600Reg<"-0.5">; def NEG_ONE : R600Reg<"-1.0">; def PV_X : R600Reg<"pv.x">; def ALU_LITERAL_X : R600Reg<"literal.x">; +def PREDICATE_BIT : R600Reg<"PredicateBit">; +def PRED_SEL_OFF: R600Reg<"Pred_sel_off">; +def PRED_SEL_ZERO : R600Reg<"Pred_sel_zero">; +def PRED_SEL_ONE : R600Reg<"Pred_sel_one">; def R600_CReg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add $creg_list)>; @@ -84,6 +88,12 @@ def R600_Reg32 : RegisterClass <"AMDGPU", [f32, i32], 32, (add R600_CReg32, ZERO, HALF, ONE, ONE_INT, PV_X, ALU_LITERAL_X, NEG_ONE, NEG_HALF)>; +def R600_Predicate : RegisterClass <"AMDGPU", [i32], 32, (add + PRED_SEL_OFF, PRED_SEL_ZERO, PRED_SEL_ONE)>; + +def R600_Predicate_Bit: RegisterClass <"AMDGPU", [i32], 32, (add + PREDICATE_BIT)>; + def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add $t128_string)> { |